git.zerfleddert.de Git - raggedstone/blob - dhwk/source/pci/config_space_header.vhd

   1 -- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007
   2
   3 LIBRARY ieee;
   4
   5 USE ieee.std_logic_1164.ALL;
   6 USE ieee.numeric_std.ALL;
   7
   8
   9 entity CONFIG_SPACE_HEADER is
  10         Port ( AD_REG : In std_logic_vector (31 downto 0);
  11                ADDR_REG : In std_logic_vector (31 downto 0);
  12                CBE_REGn : In std_logic_vector (3 downto 0);
  13                CF_RD_COM : In std_logic;
  14                CF_WR_COM : In std_logic;
  15                IRDY_REGn : In std_logic;
  16                PCI_CLOCK : In std_logic;
  17                PCI_RSTn : In std_logic;
  18                PERR : In std_logic;
  19                REVISION_ID : In std_logic_vector (7 downto 0);
  20                SERR : In std_logic;
  21                TRDYn : In std_logic;
  22                VENDOR_ID : In std_logic_vector (15 downto 0);
  23                CONF_DATA : Out std_logic_vector (31 downto 0);
  24                CONF_DATA_04H : Out std_logic_vector (31 downto 0);
  25                CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
  26 end CONFIG_SPACE_HEADER;
  27
  28 architecture SCHEMATIC of CONFIG_SPACE_HEADER is
  29
  30         constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";
  31         --other comm. device
  32         constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";
  33
  34         SIGNAL gnd : std_logic := '0';
  35         SIGNAL vcc : std_logic := '1';
  36
  37         signal CONF_WR_04H : std_logic;
  38         signal CONF_WR_10H : std_logic;
  39         signal CONF_WR_3CH : std_logic;
  40         signal CONF_READ_SEL : std_logic_vector (2 downto 0);
  41         signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);
  42         signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
  43         signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
  44         signal CONF_DATA_08H : std_logic_vector (31 downto 0);
  45         signal CONF_DATA_00H : std_logic_vector (31 downto 0);
  46
  47         component CONFIG_MUX_0
  48                 Port ( CONF_DATA_00H : In std_logic_vector (31 downto 0);
  49                        CONF_DATA_04H : In std_logic_vector (31 downto 0);
  50                        CONF_DATA_08H : In std_logic_vector (31 downto 0);
  51                        CONF_DATA_10H : In std_logic_vector (31 downto 0);
  52                        CONF_DATA_3CH : In std_logic_vector (31 downto 0);
  53                        READ_SEL : In std_logic_vector (2 downto 0);
  54                        CONF_DATA : Out std_logic_vector (31 downto 0) );
  55         end component;
  56
  57         component CONFIG_RD_0
  58                 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
  59                        CF_RD_COM : In std_logic;
  60                        READ_SEL : Out std_logic_vector (2 downto 0) );
  61         end component;
  62
  63         component CONFIG_WR_0
  64                 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
  65                        CF_WR_COM : In std_logic;
  66                        IRDY_REGn : In std_logic;
  67                        TRDYn : In std_logic;
  68                        CONF_WR_04H : Out std_logic;
  69                        CONF_WR_10H : Out std_logic;
  70                        CONF_WR_3CH : Out std_logic );
  71         end component;
  72
  73         component CONFIG_3CH
  74                 Port ( AD_REG : In std_logic_vector (31 downto 0);
  75                        CBE_REGn : In std_logic_vector (3 downto 0);
  76                        CONF_WR_3CH : In std_logic;
  77                        PCI_CLOCK : In std_logic;
  78                        PCI_RSTn : In std_logic;
  79                        CONF_DATA_3CH : Out std_logic_vector (31 downto 0) );
  80         end component;
  81
  82         component CONFIG_10H
  83                 Port ( AD_REG : In std_logic_vector (31 downto 0);
  84                        CBE_REGn : In std_logic_vector (3 downto 0);
  85                        CONF_WR_10H : In std_logic;
  86                        PCI_CLOCK : In std_logic;
  87                        PCI_RSTn : In std_logic;
  88                        CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
  89         end component;
  90
  91         component CONFIG_04H
  92                 Port ( AD_REG : In std_logic_vector (31 downto 0);
  93                        CBE_REGn : In std_logic_vector (3 downto 0);
  94                        CONF_WR_04H : In std_logic;
  95                        PCI_CLOCK : In std_logic;
  96                        PCI_RSTn : In std_logic;
  97                        PERR : In std_logic;
  98                        SERR : In std_logic;
  99                        CONF_DATA_04H : Out std_logic_vector (31 downto 0) );
 100         end component;
 101
 102 begin
 103         CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
 104         CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
 105
 106         CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
 107         CONF_DATA_10H <= CONF_DATA_10H_DUMMY;
 108
 109         I10 : CONFIG_MUX_0
 110         Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),
 111         CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),
 112         CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),
 113         CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),
 114         CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),
 115         READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),
 116         CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );
 117         I9 : CONFIG_RD_0
 118         Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
 119                    CF_RD_COM=>CF_RD_COM,
 120                    READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
 121         I8 : CONFIG_WR_0
 122         Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
 123                    CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
 124                    TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
 125                    CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
 126         I6 : CONFIG_3CH
 127         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
 128         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
 129         CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,
 130         PCI_RSTn=>PCI_RSTn,
 131         CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );
 132         I5 : CONFIG_10H
 133         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
 134         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
 135         CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,
 136         PCI_RSTn=>PCI_RSTn,
 137         CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );
 138         I2 : CONFIG_04H
 139         Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
 140         CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
 141         CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,
 142         PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
 143         CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );
 144
 145 end SCHEMATIC;