loopback
[raggedstone] / dhwk / source / top.vhd
1 -- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007
2
3
4
5 LIBRARY ieee;
6
7 USE ieee.std_logic_1164.ALL;
8 USE ieee.numeric_std.ALL;
9
10
11 entity dhwk is
12 Port ( KONST_1 : In std_logic;
13 PCI_CBEn : In std_logic_vector (3 downto 0);
14 PCI_CLOCK : In std_logic;
15 PCI_FRAMEn : In std_logic;
16 PCI_IDSEL : In std_logic;
17 PCI_IRDYn : In std_logic;
18 PCI_RSTn : In std_logic;
19 -- SERIAL_IN : In std_logic;
20 -- SPC_RDY_IN : In std_logic;
21 TAST_RESn : In std_logic;
22 TAST_SETn : In std_logic;
23 PCI_AD : InOut std_logic_vector (31 downto 0);
24 PCI_PAR : InOut std_logic;
25 PCI_DEVSELn : Out std_logic;
26 PCI_INTAn : Out std_logic;
27 PCI_PERRn : Out std_logic;
28 PCI_SERRn : Out std_logic;
29 PCI_STOPn : Out std_logic;
30 PCI_TRDYn : Out std_logic;
31 -- SERIAL_OUT : Out std_logic;
32 -- SPC_RDY_OUT : Out std_logic;
33 TB_IDSEL : Out std_logic;
34 TB_nDEVSEL : Out std_logic;
35 TB_nINTA : Out std_logic );
36 end dhwk;
37
38 architecture SCHEMATIC of dhwk is
39
40 SIGNAL gnd : std_logic := '0';
41 SIGNAL vcc : std_logic := '1';
42
43 signal READ_XX7_6 : std_logic;
44 signal RESERVE : std_logic;
45 signal SR_ERROR : std_logic;
46 signal R_ERROR : std_logic;
47 signal S_ERROR : std_logic;
48 signal WRITE_XX3_2 : std_logic;
49 signal WRITE_XX5_4 : std_logic;
50 signal WRITE_XX7_6 : std_logic;
51 signal READ_XX1_0 : std_logic;
52 signal READ_XX3_2 : std_logic;
53 signal INTAn : std_logic;
54 signal TRDYn : std_logic;
55 signal READ_XX5_4 : std_logic;
56 signal DEVSELn : std_logic;
57 signal FIFO_RDn : std_logic;
58 signal WRITE_XX1_0 : std_logic;
59 signal REG_OUT_XX6 : std_logic_vector (7 downto 0);
60 signal SYNC_FLAG : std_logic_vector (7 downto 0);
61 signal INT_REG : std_logic_vector (7 downto 0);
62 signal REVISON_ID : std_logic_vector (7 downto 0);
63 signal VENDOR_ID : std_logic_vector (15 downto 0);
64 signal READ_SEL : std_logic_vector (1 downto 0);
65 signal AD_REG : std_logic_vector (31 downto 0);
66 signal REG_OUT_XX7 : std_logic_vector (7 downto 0);
67 signal R_EFn : std_logic;
68 signal R_FFn : std_logic;
69 signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);
70 signal R_HFn : std_logic;
71 signal S_EFn : std_logic;
72 signal S_FFn : std_logic;
73 signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);
74 signal S_HFn : std_logic;
75 signal R_FIFO_D_IN : std_logic_vector (7 downto 0);
76 signal R_FIFO_READn : std_logic;
77 signal R_FIFO_RESETn : std_logic;
78 signal R_FIFO_RTn : std_logic;
79 signal R_FIFO_WRITEn : std_logic;
80 signal S_FIFO_D_IN : std_logic_vector (7 downto 0);
81 signal S_FIFO_READn : std_logic;
82 signal S_FIFO_RESETn : std_logic;
83 signal S_FIFO_RTn : std_logic;
84 signal S_FIFO_WRITEn : std_logic;
85 signal SERIAL_IN : std_logic;
86 signal SPC_RDY_IN : std_logic;
87 signal SERIAL_OUT : std_logic;
88 signal SPC_RDY_OUT : std_logic;
89
90 component MESS_1_TB
91 Port ( DEVSELn : In std_logic;
92 INTAn : In std_logic;
93 KONST_1 : In std_logic;
94 PCI_IDSEL : In std_logic;
95 REG_OUT_XX7 : In std_logic_vector (7 downto 0);
96 TB_DEVSELn : Out std_logic;
97 TB_INTAn : Out std_logic;
98 TB_PCI_IDSEL : Out std_logic );
99 end component;
100
101 component VEN_REV_ID
102 Port ( REV_ID : Out std_logic_vector (7 downto 0);
103 VEN_ID : Out std_logic_vector (15 downto 0) );
104 end component;
105
106 component INTERRUPT
107 Port ( INT_IN_0 : In std_logic;
108 INT_IN_1 : In std_logic;
109 INT_IN_2 : In std_logic;
110 INT_IN_3 : In std_logic;
111 INT_IN_4 : In std_logic;
112 INT_IN_5 : In std_logic;
113 INT_IN_6 : In std_logic;
114 INT_IN_7 : In std_logic;
115 INT_MASKE : In std_logic_vector (7 downto 0);
116 INT_RES : In std_logic_vector (7 downto 0);
117 PCI_CLOCK : In std_logic;
118 PCI_RSTn : In std_logic;
119 READ_XX5_4 : In std_logic;
120 RESET : In std_logic;
121 TAST_RESn : In std_logic;
122 TAST_SETn : In std_logic;
123 TRDYn : In std_logic;
124 INT_REG : Out std_logic_vector (7 downto 0);
125 INTAn : Out std_logic;
126 PCI_INTAn : Out std_logic );
127 end component;
128
129 component FIFO_CONTROL
130 Port ( FIFO_RDn : In std_logic;
131 FLAG_IN_0 : In std_logic;
132 FLAG_IN_4 : In std_logic;
133 HOLD : In std_logic;
134 KONST_1 : In std_logic;
135 PCI_CLOCK : In std_logic;
136 PSC_ENABLE : In std_logic;
137 R_EFn : In std_logic;
138 R_FFn : In std_logic;
139 R_HFn : In std_logic;
140 RESET : In std_logic;
141 S_EFn : In std_logic;
142 S_FFn : In std_logic;
143 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
144 S_HFn : In std_logic;
145 SERIAL_IN : In std_logic;
146 SPC_ENABLE : In std_logic;
147 SPC_RDY_IN : In std_logic;
148 WRITE_XX1_0 : In std_logic;
149 R_ERROR : Out std_logic;
150 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
151 R_FIFO_READn : Out std_logic;
152 R_FIFO_RESETn : Out std_logic;
153 R_FIFO_RETRANSMITn : Out std_logic;
154 R_FIFO_WRITEn : Out std_logic;
155 RESERVE : Out std_logic;
156 S_ERROR : Out std_logic;
157 S_FIFO_READn : Out std_logic;
158 S_FIFO_RESETn : Out std_logic;
159 S_FIFO_RETRANSMITn : Out std_logic;
160 S_FIFO_WRITEn : Out std_logic;
161 SERIAL_OUT : Out std_logic;
162 SPC_RDY_OUT : Out std_logic;
163 SR_ERROR : Out std_logic;
164 SYNC_FLAG : Out std_logic_vector (7 downto 0) );
165 end component;
166
167 component PCI_TOP
168 Port ( FLAG : In std_logic_vector (7 downto 0);
169 INT_REG : In std_logic_vector (7 downto 0);
170 PCI_CBEn : In std_logic_vector (3 downto 0);
171 PCI_CLOCK : In std_logic;
172 PCI_FRAMEn : In std_logic;
173 PCI_IDSEL : In std_logic;
174 PCI_IRDYn : In std_logic;
175 PCI_RSTn : In std_logic;
176 R_FIFO_Q : In std_logic_vector (7 downto 0);
177 REVISON_ID : In std_logic_vector (7 downto 0);
178 VENDOR_ID : In std_logic_vector (15 downto 0);
179 PCI_AD : InOut std_logic_vector (31 downto 0);
180 PCI_PAR : InOut std_logic;
181 AD_REG : Out std_logic_vector (31 downto 0);
182 DEVSELn : Out std_logic;
183 FIFO_RDn : Out std_logic;
184 PCI_DEVSELn : Out std_logic;
185 PCI_PERRn : Out std_logic;
186 PCI_SERRn : Out std_logic;
187 PCI_STOPn : Out std_logic;
188 PCI_TRDYn : Out std_logic;
189 READ_SEL : Out std_logic_vector (1 downto 0);
190 READ_XX1_0 : Out std_logic;
191 READ_XX3_2 : Out std_logic;
192 READ_XX5_4 : Out std_logic;
193 READ_XX7_6 : Out std_logic;
194 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
195 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
196 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
197 TRDYn : Out std_logic;
198 WRITE_XX1_0 : Out std_logic;
199 WRITE_XX3_2 : Out std_logic;
200 WRITE_XX5_4 : Out std_logic;
201 WRITE_XX7_6 : Out std_logic );
202 end component;
203
204 component fifo_generator_v3_2
205 port (
206 clk: IN std_logic;
207 din: IN std_logic_VECTOR(7 downto 0);
208 rd_en: IN std_logic;
209 rst: IN std_logic;
210 wr_en: IN std_logic;
211 almost_empty: OUT std_logic;
212 almost_full: OUT std_logic;
213 dout: OUT std_logic_VECTOR(7 downto 0);
214 empty: OUT std_logic;
215 full: OUT std_logic;
216 prog_full: OUT std_logic);
217 end component;
218
219 begin
220 SERIAL_IN <= SERIAL_OUT;
221 SPC_RDY_IN <= SPC_RDY_OUT;
222
223 I19 : MESS_1_TB
224 Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
225 PCI_IDSEL=>PCI_IDSEL,
226 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
227 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,
228 TB_PCI_IDSEL=>TB_IDSEL );
229 I18 : VEN_REV_ID
230 Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),
231 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );
232 I16 : INTERRUPT
233 Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),
234 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,
235 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,
236 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),
237 INT_RES(7 downto 0)=>AD_REG(7 downto 0),
238 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
239 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
240 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
241 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
242 INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );
243 I14 : FIFO_CONTROL
244 Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
245 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
246 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),
247 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,
248 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,
249 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
250 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,
251 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,
252 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
253 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
254 R_FIFO_READn=>R_FIFO_READn,
255 R_FIFO_RESETn=>R_FIFO_RESETn,
256 R_FIFO_RETRANSMITn=>R_FIFO_RTn,
257 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,
258 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,
259 S_FIFO_RESETn=>S_FIFO_RESETn,
260 S_FIFO_RETRANSMITn=>S_FIFO_RTn,
261 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
262 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
263 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
264 I1 : PCI_TOP
265 Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
266 INT_REG(7 downto 0)=>INT_REG(7 downto 0),
267 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
268 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
269 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
270 PCI_RSTn=>PCI_RSTn,
271 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),
272 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
273 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
274 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
275 PCI_PAR=>PCI_PAR,
276 AD_REG(31 downto 0)=>AD_REG(31 downto 0),
277 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
278 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
279 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
280 PCI_TRDYn=>PCI_TRDYn,
281 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
282 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
283 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
284 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),
285 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
286 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
287 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,
288 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
289 WRITE_XX7_6=>WRITE_XX7_6 );
290
291 receive_fifo : fifo_generator_v3_2
292 port map (
293 clk => PCI_CLOCK,
294 din => R_FIFO_D_IN,
295 rd_en => not R_FIFO_READn,
296 rst => not R_FIFO_RESETn,
297 wr_en => not R_FIFO_WRITEn,
298 dout => R_FIFO_Q_OUT,
299 empty => R_EFn,
300 full => R_FFn,
301 prog_full => R_HFn);
302
303 send_fifo : fifo_generator_v3_2
304 port map (
305 clk => PCI_CLOCK,
306 din => S_FIFO_D_IN,
307 rd_en => not S_FIFO_READn,
308 rst => not S_FIFO_RESETn,
309 wr_en => not S_FIFO_WRITEn,
310 dout => S_FIFO_Q_OUT,
311 empty => S_EFn,
312 full => S_FFn,
313 prog_full => S_HFn);
314 end SCHEMATIC;
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