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1 //////////////////////////////////////////////////////////////////////
2 //// ////
3 //// File name "bus_commands.v" ////
4 //// ////
5 //// This file is part of the "PCI bridge" project ////
6 //// http://www.opencores.org/cores/pci/ ////
7 //// ////
8 //// Author(s): ////
9 //// - Miha Dolenc (mihad@opencores.org) ////
10 //// ////
11 //// All additional information is avaliable in the README.pdf ////
12 //// file. ////
13 //// ////
14 //// ////
15 //////////////////////////////////////////////////////////////////////
16 //// ////
17 //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
18 //// ////
19 //// This source file may be used and distributed without ////
20 //// restriction provided that this copyright statement is not ////
21 //// removed from the file and that any derivative work contains ////
22 //// the original copyright notice and the associated disclaimer. ////
23 //// ////
24 //// This source file is free software; you can redistribute it ////
25 //// and/or modify it under the terms of the GNU Lesser General ////
26 //// Public License as published by the Free Software Foundation; ////
27 //// either version 2.1 of the License, or (at your option) any ////
28 //// later version. ////
29 //// ////
30 //// This source is distributed in the hope that it will be ////
31 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
33 //// PURPOSE. See the GNU Lesser General Public License for more ////
34 //// details. ////
35 //// ////
36 //// You should have received a copy of the GNU Lesser General ////
37 //// Public License along with this source; if not, download it ////
38 //// from http://www.opencores.org/lgpl.shtml ////
39 //// ////
40 //////////////////////////////////////////////////////////////////////
41 //
42 // CVS Revision History
43 //
44 // $Log: bus_commands.v,v $
45 // Revision 1.1 2007-03-20 17:50:56 sithglan
46 // add shit
47 //
48 // Revision 1.4 2002/08/22 13:28:05 mihad
49 // Updated for synthesis purposes. Gate level simulation was failing in some configurations
50 //
51 // Revision 1.3 2002/02/01 15:25:12 mihad
52 // Repaired a few bugs, updated specification, added test bench files and design document
53 //
54 // Revision 1.2 2001/10/05 08:14:28 mihad
55 // Updated all files with inclusion of timescale file for simulation purposes.
56 //
57 // Revision 1.1.1.1 2001/10/02 15:33:47 mihad
58 // New project directory structure
59 //
60 //
61
62 // definitions of PCI bus commands | used by PCI Master | used by PCI Target
63 `define BC_IACK 4'h0 // yes no
64 `define BC_SPECIAL 4'h1 // no no
65 `define BC_IO_READ 4'h2 // yes yes
66 `define BC_IO_WRITE 4'h3 // yes yes
67 `define BC_RESERVED0 4'h4 // no no
68 `define BC_RESERVED1 4'h5 // no no
69 `define BC_MEM_READ 4'h6 // yes yes
70 `define BC_MEM_WRITE 4'h7 // yes yes
71 `define BC_RESERVED2 4'h8 // no no
72 `define BC_RESERVED3 4'h9 // no no
73 `define BC_CONF_READ 4'hA // yes yes
74 `define BC_CONF_WRITE 4'hB // yes yes
75 `define BC_MEM_READ_MUL 4'hC // yes yes
76 `define BC_DUAL_ADDR_CYC 4'hD // no no
77 `define BC_MEM_READ_LN 4'hE // yes yes
78 `define BC_MEM_WRITE_INVAL 4'hF // no yes
79
80 // common bits for configuration cycle commands
81 `define BC_CONF_RW 3'b101
82 // common bits for io cycle commands
83 `define BC_IO_RW 3'b001
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