git.zerfleddert.de Git - raggedstone/blob - ethernet/source/ethernet/eth_rxstatem.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  eth_rxstatem.v                                              ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects/ethmac/                   ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Igor Mohor (igorM@opencores.org)                      ////
  10 ////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
  11 ////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
  12 ////                                                              ////
  13 ////  All additional information is avaliable in the Readme.txt   ////
  14 ////  file.                                                       ////
  15 ////                                                              ////
  16 //////////////////////////////////////////////////////////////////////
  17 ////                                                              ////
  18 //// Copyright (C) 2001 Authors                                   ////
  19 ////                                                              ////
  20 //// This source file may be used and distributed without         ////
  21 //// restriction provided that this copyright statement is not    ////
  22 //// removed from the file and that any derivative work contains  ////
  23 //// the original copyright notice and the associated disclaimer. ////
  24 ////                                                              ////
  25 //// This source file is free software; you can redistribute it   ////
  26 //// and/or modify it under the terms of the GNU Lesser General   ////
  27 //// Public License as published by the Free Software Foundation; ////
  28 //// either version 2.1 of the License, or (at your option) any   ////
  29 //// later version.                                               ////
  30 ////                                                              ////
  31 //// This source is distributed in the hope that it will be       ////
  32 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  33 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  34 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  35 //// details.                                                     ////
  36 ////                                                              ////
  37 //// You should have received a copy of the GNU Lesser General    ////
  38 //// Public License along with this source; if not, download it   ////
  39 //// from http://www.opencores.org/lgpl.shtml                     ////
  40 ////                                                              ////
  41 //////////////////////////////////////////////////////////////////////
  42 //
  43 // CVS Revision History
  44 //
  45 // $Log: eth_rxstatem.v,v $
  46 // Revision 1.1  2007-03-20 17:50:56  sithglan
  47 // add shit
  48 //
  49 // Revision 1.6  2002/11/13 22:28:26  tadejm
  50 // StartIdle state changed (not important the size of the packet).
  51 // StartData1 activates only while ByteCnt is smaller than the MaxFrame.
  52 //
  53 // Revision 1.5  2002/01/23 10:28:16  mohor
  54 // Link in the header changed.
  55 //
  56 // Revision 1.4  2001/10/19 08:43:51  mohor
  57 // eth_timescale.v changed to timescale.v This is done because of the
  58 // simulation of the few cores in a one joined project.
  59 //
  60 // Revision 1.3  2001/10/18 12:07:11  mohor
  61 // Status signals changed, Adress decoding changed, interrupt controller
  62 // added.
  63 //
  64 // Revision 1.2  2001/09/11 14:17:00  mohor
  65 // Few little NCSIM warnings fixed.
  66 //
  67 // Revision 1.1  2001/08/06 14:44:29  mohor
  68 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
  69 // Include files fixed to contain no path.
  70 // File names and module names changed ta have a eth_ prologue in the name.
  71 // File eth_timescale.v is used to define timescale
  72 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
  73 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
  74 // and Mdo_OE. The bidirectional signal must be created on the top level. This
  75 // is done due to the ASIC tools.
  76 //
  77 // Revision 1.1  2001/07/30 21:23:42  mohor
  78 // Directory structure changed. Files checked and joind together.
  79 //
  80 // Revision 1.2  2001/07/03 12:55:41  mohor
  81 // Minor changes because of the synthesys warnings.
  82 //
  83 //
  84 // Revision 1.1  2001/06/27 21:26:19  mohor
  85 // Initial release of the RxEthMAC module.
  86 //
  87 //
  88 //
  89 //
  90
  91
  92 `include "timescale.v"
  93
  94
  95 module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
  96                      IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
  97                      StateDrop
  98                     );
  99
 100 parameter Tp = 1;
 101
 102 input         MRxClk;
 103 input         Reset;
 104 input         MRxDV;
 105 input         ByteCntEq0;
 106 input         ByteCntGreat2;
 107 input         MRxDEq5;
 108 input         Transmitting;
 109 input         MRxDEqD;
 110 input         IFGCounterEq24;
 111 input         ByteCntMaxFrame;
 112
 113 output [1:0]  StateData;
 114 output        StateIdle;
 115 output        StateDrop;
 116 output        StatePreamble;
 117 output        StateSFD;
 118
 119 reg           StateData0;
 120 reg           StateData1;
 121 reg           StateIdle;
 122 reg           StateDrop;
 123 reg           StatePreamble;
 124 reg           StateSFD;
 125
 126 wire          StartIdle;
 127 wire          StartDrop;
 128 wire          StartData0;
 129 wire          StartData1;
 130 wire          StartPreamble;
 131 wire          StartSFD;
 132
 133
 134 // Defining the next state
 135 assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
 136
 137 assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
 138
 139 assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
 140
 141 assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
 142
 143 assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
 144
 145 assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 &  MRxDEqD
 146                          |  StateData0 &  ByteCntMaxFrame
 147                            );
 148
 149 // Rx State Machine
 150 always @ (posedge MRxClk or posedge Reset)
 151 begin
 152   if(Reset)
 153     begin
 154       StateIdle     <= #Tp 1'b0;
 155       StateDrop     <= #Tp 1'b1;
 156       StatePreamble <= #Tp 1'b0;
 157       StateSFD      <= #Tp 1'b0;
 158       StateData0    <= #Tp 1'b0;
 159       StateData1    <= #Tp 1'b0;
 160     end
 161   else
 162     begin
 163       if(StartPreamble | StartSFD | StartDrop)
 164         StateIdle <= #Tp 1'b0;
 165       else
 166       if(StartIdle)
 167         StateIdle <= #Tp 1'b1;
 168
 169       if(StartIdle)
 170         StateDrop <= #Tp 1'b0;
 171       else
 172       if(StartDrop)
 173         StateDrop <= #Tp 1'b1;
 174
 175       if(StartSFD | StartIdle | StartDrop)
 176         StatePreamble <= #Tp 1'b0;
 177       else
 178       if(StartPreamble)
 179         StatePreamble <= #Tp 1'b1;
 180
 181       if(StartPreamble | StartIdle | StartData0 | StartDrop)
 182         StateSFD <= #Tp 1'b0;
 183       else
 184       if(StartSFD)
 185         StateSFD <= #Tp 1'b1;
 186
 187       if(StartIdle | StartData1 | StartDrop)
 188         StateData0 <= #Tp 1'b0;
 189       else
 190       if(StartData0)
 191         StateData0 <= #Tp 1'b1;
 192
 193       if(StartIdle | StartData0 | StartDrop)
 194         StateData1 <= #Tp 1'b0;
 195       else
 196       if(StartData1)
 197         StateData1 <= #Tp 1'b1;
 198     end
 199 end
 200
 201 assign StateData[1:0] = {StateData1, StateData0};
 202
 203 endmodule