git.zerfleddert.de Git - raggedstone/blob - ethernet/source/pci/pci_target32_clk_en.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  File name: pci_target32_clk_en.v                            ////
   4 ////                                                              ////
   5 ////  This file is part of the "PCI bridge" project               ////
   6 ////  http://www.opencores.org/cores/pci/                         ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Tadej Markovic, tadej@opencores.org                   ////
  10 ////                                                              ////
  11 ////  All additional information is avaliable in the README.txt   ////
  12 ////  file.                                                       ////
  13 ////                                                              ////
  14 ////                                                              ////
  15 //////////////////////////////////////////////////////////////////////
  16 ////                                                              ////
  17 //// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org       ////
  18 ////                                                              ////
  19 //// This source file may be used and distributed without         ////
  20 //// restriction provided that this copyright statement is not    ////
  21 //// removed from the file and that any derivative work contains  ////
  22 //// the original copyright notice and the associated disclaimer. ////
  23 ////                                                              ////
  24 //// This source file is free software; you can redistribute it   ////
  25 //// and/or modify it under the terms of the GNU Lesser General   ////
  26 //// Public License as published by the Free Software Foundation; ////
  27 //// either version 2.1 of the License, or (at your option) any   ////
  28 //// later version.                                               ////
  29 ////                                                              ////
  30 //// This source is distributed in the hope that it will be       ////
  31 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  33 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  34 //// details.                                                     ////
  35 ////                                                              ////
  36 //// You should have received a copy of the GNU Lesser General    ////
  37 //// Public License along with this source; if not, download it   ////
  38 //// from http://www.opencores.org/lgpl.shtml                     ////
  39 ////                                                              ////
  40 //////////////////////////////////////////////////////////////////////
  41 //
  42 // CVS Revision History
  43 //
  44 // $Log: pci_target32_clk_en.v,v $
  45 // Revision 1.1  2007-03-20 17:50:56  sithglan
  46 // add shit
  47 //
  48 // Revision 1.4  2003/01/27 16:49:31  mihad
  49 // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
  50 //
  51 // Revision 1.3  2002/02/01 15:25:12  mihad
  52 // Repaired a few bugs, updated specification, added test bench files and design document
  53 //
  54 // Revision 1.2  2001/10/05 08:14:30  mihad
  55 // Updated all files with inclusion of timescale file for simulation purposes.
  56 //
  57 // Revision 1.1.1.1  2001/10/02 15:33:47  mihad
  58 // New project directory structure
  59 //
  60 //
  61
  62 // module is used to separate logic which uses criticaly constrained inputs from slower logic.
  63 // It is used to synthesize critical timing logic separately with faster cells or without optimization
  64
  65 // synopsys translate_off
  66 `include "timescale.v"
  67 // synopsys translate_on
  68
  69 module pci_target32_clk_en
  70 (
  71     addr_phase,
  72     config_access,
  73     addr_claim_in,
  74     pci_frame_in,
  75     state_wait,
  76     state_transfere,
  77     state_default,
  78     clk_enable
  79 );
  80
  81 input           addr_phase ;                    // indicates registered address phase on PCI bus
  82 input           config_access ;                 // indicates configuration access
  83 input           addr_claim_in ;                 // indicates claimed input PCI address
  84 input           pci_frame_in ;                  // critical constrained input signal
  85 input                   state_wait ;                    // indicates WAIT state of FSM
  86 input                   state_transfere ;               // indicates TRANSFERE state of FSM
  87 input                   state_default ;                 // indicates DEFAULT state of FSM
  88
  89 output                  clk_enable ;                    // FSM clock enable output
  90
  91
  92 // clock enable signal when FSM is in IDLE state
  93 wire s_idle_clk_en      =       ((addr_phase && config_access) ||
  94                                                 (addr_phase && ~config_access && addr_claim_in)) ;
  95
  96 // clock enable signal when FSM is in WAIT state or in DEFAULT state
  97 wire s_wait_clk_en      =       (state_wait || state_default) ;
  98
  99 // clock enable signal when FSM is in TRANSFERE state
 100 wire s_tran_clk_en      =       (state_transfere && pci_frame_in) ;
 101
 102
 103 // Clock enable signal for FSM with preserved hierarchy for minimum delay!
 104 assign clk_enable       =       (s_idle_clk_en || s_wait_clk_en || s_tran_clk_en) ;
 105
 106
 107 endmodule