git.zerfleddert.de Git - raggedstone/blob - dhwk/source/pci/config_3Ch.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 23.08.2006
   4 -- File: CONFIG_3CH.VHD
   5
   6 library IEEE;
   7 use IEEE.std_logic_1164.all;
   8
   9 entity CONFIG_3CH is
  10         port (
  11                      PCI_CLOCK :in std_logic;
  12                      PCI_RSTn :in std_logic;
  13                      AD_REG :in std_logic_vector (31 downto 0);
  14                      CBE_REGn :in std_logic_vector ( 3 downto 0);
  15                      CONF_WR_3CH :in std_logic;
  16                      CONF_DATA_3CH :out std_logic_vector (31 downto 0)
  17              );
  18 end entity CONFIG_3CH;
  19
  20 architecture CONFIG_3CH_DESIGN of CONFIG_3CH is
  21
  22  -- PCI Configuration Space Header Addr : HEX 3C --
  23
  24         signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
  25         signal CONF_MIN_GNT :std_logic_vector (23 downto 16);
  26         signal CONF_INT_PIN :std_logic_vector (15 downto 8);
  27         signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);
  28
  29         constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011";
  30 begin
  31
  32  --*******************************************************************
  33  --*********** PCI Configuration Space Header "INTERRUPT" ************
  34  --*******************************************************************
  35
  36         CONF_MAX_LAT <= X"00";
  37         CONF_MIN_GNT <= X"00";
  38         -- CONF_INT_PIN <= X"00"; -- Interrupt -
  39         CONF_INT_PIN <= X"01"; -- Interrupt A
  40         -- CONF_INT_PIN <= X"02"; -- Interrupt B
  41         -- CONF_INT_PIN <= X"03"; -- Interrupt C
  42         -- CONF_INT_PIN <= X"04"; -- Interrupt D
  43         -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
  44
  45         process (PCI_CLOCK,PCI_RSTn)
  46         begin
  47                 if PCI_RSTn = '0' then
  48                         CONF_INT_LINE <= (others => '0');
  49
  50                 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
  51                         if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
  52                                 CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
  53                         end if;
  54                 end if;
  55         end process;
  56
  57         CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
  58
  59 end architecture CONFIG_3CH_DESIGN;