1 -- $Id: SER_PAR_CON.vhd,v 1.2 2007-03-11 08:04:56 sithglan Exp $
4 use ieee.std_logic_1164.all;
5 use ieee.std_logic_unsigned.all;
10 PCI_CLOCK :in std_logic;
12 SPC_ENABLE :in std_logic; -- Driver Enable Sender/Receiver
13 SYNC_R_FIFO_FFn :in std_logic; -- FIFO Full Flag (low active)
14 SERIAL_IN :in std_logic; -- Serial Input
15 R_FIFO_WRITEn :out std_logic; -- FIFO Write (low active)
16 SPC_RDY_OUT :out std_logic; -- Ready to Receive Data
17 PAR_OUT :out std_logic_vector(7 downto 0)
19 end entity SER_PAR_CON ;
22 architecture SER_PAR_CON_DESIGN of SER_PAR_CON is
24 -- constant STATE_RECV :std_logic_vector(3 downto 0) := "0001";
25 constant STATE_RECV_START_BIT :std_logic_vector(3 downto 0) := "0010";
26 constant STATE_RECV_BIT_0 :std_logic_vector(3 downto 0) := "0011";
27 constant STATE_RECV_BIT_1 :std_logic_vector(3 downto 0) := "0100";
28 constant STATE_RECV_BIT_2 :std_logic_vector(3 downto 0) := "0101";
29 constant STATE_RECV_BIT_3 :std_logic_vector(3 downto 0) := "0110";
30 constant STATE_RECV_BIT_4 :std_logic_vector(3 downto 0) := "0111";
31 constant STATE_RECV_BIT_5 :std_logic_vector(3 downto 0) := "1000";
32 constant STATE_RECV_BIT_6 :std_logic_vector(3 downto 0) := "1001";
33 constant STATE_RECV_BIT_7 :std_logic_vector(3 downto 0) := "1010";
34 constant STATE_RECV_FIFOFULL :std_logic_vector(3 downto 0) := "1011";
36 signal COUNT :std_logic_vector (3 downto 0);
37 signal STATE :std_logic_vector (3 downto 0);
38 signal STARTBIT :std_logic_vector (3 downto 0);
41 attribute syn_state_machine:boolean;
42 attribute syn_state_machine of STATE: signal is false;
43 attribute syn_state_machine of COUNT: signal is false;
49 if (PCI_CLOCK'event and PCI_CLOCK = '1') then
50 if ("0000" < COUNT) then
54 -- war nicht das Problem des Datenverlusts
55 -- if (R_FIFO_WRITEn = '0' and COUNT = "0000") then
56 -- R_FIFO_WRITEn <= '1';
60 STATE <= STATE_RECV_START_BIT;
64 elsif (SPC_ENABLE = '1') then
66 if (STATE = STATE_RECV_START_BIT) then
68 if (STARTBIT = "0011") then
70 STATE <= STATE_RECV_BIT_0;
73 elsif (STATE = STATE_RECV_FIFOFULL) then
74 if (SYNC_R_FIFO_FFn = '1') then
76 STATE <= STATE_RECV_START_BIT;
79 elsif (COUNT = "0000") then
83 when STATE_RECV_BIT_0 =>
84 PAR_OUT(0) <= STARTBIT(0);
85 STATE <= STATE_RECV_BIT_1;
87 when STATE_RECV_BIT_1 =>
88 PAR_OUT(1) <= STARTBIT(0);
89 STATE <= STATE_RECV_BIT_2;
91 when STATE_RECV_BIT_2 =>
92 PAR_OUT(2) <= STARTBIT(0);
93 STATE <= STATE_RECV_BIT_3;
95 when STATE_RECV_BIT_3 =>
96 PAR_OUT(3) <= STARTBIT(0);
97 STATE <= STATE_RECV_BIT_4;
99 when STATE_RECV_BIT_4 =>
100 PAR_OUT(4) <= STARTBIT(0);
101 STATE <= STATE_RECV_BIT_5;
103 when STATE_RECV_BIT_5 =>
104 PAR_OUT(5) <= STARTBIT(0);
105 STATE <= STATE_RECV_BIT_6;
107 when STATE_RECV_BIT_6 =>
108 PAR_OUT(6) <= STARTBIT(0);
109 STATE <= STATE_RECV_BIT_7;
111 when STATE_RECV_BIT_7 =>
112 PAR_OUT(7) <= STARTBIT(0);
114 if (SYNC_R_FIFO_FFn = '1') then
115 STATE <= STATE_RECV_START_BIT;
116 R_FIFO_WRITEn <= '0';
118 STATE <= STATE_RECV_FIFOFULL;
122 STATE <= STATE_RECV_START_BIT;
126 end if; -- RESET ... / SPC_ENABLE ...
127 end if; -- PCI_CLOCK ...
132 if (PCI_CLOCK'event and PCI_CLOCK = '1') then
133 SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;
140 if (PCI_CLOCK'event and PCI_CLOCK = '1') then
141 if (RESET = '1') then
144 STARTBIT(0) <= SERIAL_IN;
145 STARTBIT(1) <= STARTBIT(0);
146 STARTBIT(2) <= STARTBIT(1);
147 STARTBIT(3) <= STARTBIT(2);
154 end architecture SER_PAR_CON_DESIGN;