git.zerfleddert.de Git - raggedstone/blob - dhwk/source/parity.vhd

   1 -- VHDL model created from schematic parity.sch -- Jan 09 09:34:12 2007
   2
   3 --LIBRARY vanmacro;
   4 --USE vanmacro.components.ALL;
   5 LIBRARY ieee;
   6 --LIBRARY generics;
   7 USE ieee.std_logic_1164.ALL;
   8 USE ieee.numeric_std.ALL;
   9 --USE generics.components.ALL;
  10
  11 entity PARITY is
  12       Port ( OE_PCI_PAR : In    std_logic;
  13              OE_PCI_PERR : In    std_logic;
  14              PA_ER_RE : In    std_logic;
  15               PAR_IN : In    std_logic_vector (35 downto 0);
  16              PAR_REG : In    std_logic;
  17              PCI_CLOCK : In    std_logic;
  18              PCI_RSTn : In    std_logic;
  19              PERR_CHECK : In    std_logic;
  20              SERR_CHECK : In    std_logic;
  21              SERR_ENA : In    std_logic;
  22              PCI_PAR : InOut std_logic;
  23              PCI_PERRn : Out   std_logic;
  24              PCI_SERRn : Out   std_logic;
  25                 PERR : Out   std_logic;
  26                 SERR : Out   std_logic );
  27 end PARITY;
  28
  29 architecture SCHEMATIC of PARITY is
  30
  31    SIGNAL gnd : std_logic := '0';
  32    SIGNAL vcc : std_logic := '1';
  33
  34    signal  PAR_OUT : std_logic_vector (10 downto 0);
  35
  36    component PARITY_OUT
  37       Port ( OE_PCI_PAR : In    std_logic;
  38              OE_PCI_PERR : In    std_logic;
  39              PA_ER_RE : In    std_logic;
  40               PAR_IN : In    std_logic_vector (2 downto 0);
  41              PAR_REG : In    std_logic;
  42              PCI_CLOCK : In    std_logic;
  43              PCI_PAR_IN : In    std_logic;
  44              PCI_RSTn : In    std_logic;
  45              PERR_CHECK : In    std_logic;
  46              SERR_CHECK : In    std_logic;
  47              SERR_ENA : In    std_logic;
  48              PCI_PAR : Out   std_logic;
  49              PCI_PERRn : Out   std_logic;
  50              PCI_SERRn : Out   std_logic;
  51                 PERR : Out   std_logic;
  52                 SERR : Out   std_logic );
  53    end component;
  54
  55    component PARITY_4
  56       Port (  PAR_IN : In    std_logic_vector (3 downto 0);
  57              PAR_OUT : Out   std_logic );
  58    end component;
  59
  60 begin
  61
  62    I12 : PARITY_OUT
  63       Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,
  64                  PA_ER_RE=>PA_ER_RE,
  65                  PAR_IN(2 downto 0)=>PAR_OUT(10 downto 8),
  66                  PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,
  67                  PCI_PAR_IN=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
  68                  PERR_CHECK=>PERR_CHECK, SERR_CHECK=>SERR_CHECK,
  69                  SERR_ENA=>SERR_ENA, PCI_PAR=>PCI_PAR,
  70                  PCI_PERRn=>PCI_PERRn, PCI_SERRn=>PCI_SERRn, PERR=>PERR,
  71                  SERR=>SERR );
  72    I9 : PARITY_4
  73       Port Map ( PAR_IN(3 downto 0)=>PAR_IN(35 downto 32),
  74                  PAR_OUT=>PAR_OUT(8) );
  75    I11 : PARITY_4
  76       Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(7 downto 4),
  77                  PAR_OUT=>PAR_OUT(10) );
  78    I8 : PARITY_4
  79       Port Map ( PAR_IN(3 downto 0)=>PAR_IN(31 downto 28),
  80                  PAR_OUT=>PAR_OUT(7) );
  81    I7 : PARITY_4
  82       Port Map ( PAR_IN(3 downto 0)=>PAR_IN(27 downto 24),
  83                  PAR_OUT=>PAR_OUT(6) );
  84    I6 : PARITY_4
  85       Port Map ( PAR_IN(3 downto 0)=>PAR_IN(23 downto 20),
  86                  PAR_OUT=>PAR_OUT(5) );
  87    I5 : PARITY_4
  88       Port Map ( PAR_IN(3 downto 0)=>PAR_IN(19 downto 16),
  89                  PAR_OUT=>PAR_OUT(4) );
  90    I4 : PARITY_4
  91       Port Map ( PAR_IN(3 downto 0)=>PAR_IN(15 downto 12),
  92                  PAR_OUT=>PAR_OUT(3) );
  93    I3 : PARITY_4
  94       Port Map ( PAR_IN(3 downto 0)=>PAR_IN(11 downto 8),
  95                  PAR_OUT=>PAR_OUT(2) );
  96    I2 : PARITY_4
  97       Port Map ( PAR_IN(3 downto 0)=>PAR_IN(7 downto 4),
  98                  PAR_OUT=>PAR_OUT(1) );
  99    I1 : PARITY_4
 100       Port Map ( PAR_IN(3 downto 0)=>PAR_IN(3 downto 0),
 101                  PAR_OUT=>PAR_OUT(0) );
 102    I10 : PARITY_4
 103       Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(3 downto 0),
 104                  PAR_OUT=>PAR_OUT(9) );
 105
 106 end SCHEMATIC;