git.zerfleddert.de Git - raggedstone/blob - dhwk/ila.xco

   1 # BEGIN Project Options
   2 SET addpads = False
   3 SET asysymbol = False
   4 SET busformat = BusFormatAngleBracketNotRipped
   5 SET createndf = False
   6 SET designentry = VHDL
   7 SET device = xc3s1500
   8 SET devicefamily = spartan3
   9 SET flowvendor = Other
  10 SET formalverification = False
  11 SET foundationsym = False
  12 SET implementationfiletype = Ngc
  13 SET package = fg456
  14 SET removerpms = False
  15 SET simulationfiles = Structural
  16 SET speedgrade = -4
  17 SET verilogsim = False
  18 SET vhdlsim = True
  19 # END Project Options
  20 # BEGIN Select
  21 SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.02.a
  22 # END Select
  23 # BEGIN Parameters
  24 CSET component_name=ila
  25 CSET counter_width_1=Disabled
  26 CSET counter_width_10=Disabled
  27 CSET counter_width_11=Disabled
  28 CSET counter_width_12=Disabled
  29 CSET counter_width_13=Disabled
  30 CSET counter_width_14=Disabled
  31 CSET counter_width_15=Disabled
  32 CSET counter_width_16=Disabled
  33 CSET counter_width_2=Disabled
  34 CSET counter_width_3=Disabled
  35 CSET counter_width_4=Disabled
  36 CSET counter_width_5=Disabled
  37 CSET counter_width_6=Disabled
  38 CSET counter_width_7=Disabled
  39 CSET counter_width_8=Disabled
  40 CSET counter_width_9=Disabled
  41 CSET data_port_width=96
  42 CSET data_same_as_trigger=false
  43 CSET enable_storage_qualification=true
  44 CSET enable_trigger_output_port=false
  45 CSET exclude_from_data_storage_1=true
  46 CSET exclude_from_data_storage_10=true
  47 CSET exclude_from_data_storage_11=true
  48 CSET exclude_from_data_storage_12=true
  49 CSET exclude_from_data_storage_13=true
  50 CSET exclude_from_data_storage_14=true
  51 CSET exclude_from_data_storage_15=true
  52 CSET exclude_from_data_storage_16=true
  53 CSET exclude_from_data_storage_2=true
  54 CSET exclude_from_data_storage_3=true
  55 CSET exclude_from_data_storage_4=true
  56 CSET exclude_from_data_storage_5=true
  57 CSET exclude_from_data_storage_6=true
  58 CSET exclude_from_data_storage_7=true
  59 CSET exclude_from_data_storage_8=true
  60 CSET exclude_from_data_storage_9=true
  61 CSET match_type_1=basic
  62 CSET match_type_10=basic
  63 CSET match_type_11=basic
  64 CSET match_type_12=basic
  65 CSET match_type_13=basic
  66 CSET match_type_14=basic
  67 CSET match_type_15=basic
  68 CSET match_type_16=basic
  69 CSET match_type_2=basic
  70 CSET match_type_3=basic
  71 CSET match_type_4=basic
  72 CSET match_type_5=basic
  73 CSET match_type_6=basic
  74 CSET match_type_7=basic
  75 CSET match_type_8=basic
  76 CSET match_type_9=basic
  77 CSET match_units_1=1
  78 CSET match_units_10=1
  79 CSET match_units_11=1
  80 CSET match_units_12=1
  81 CSET match_units_13=1
  82 CSET match_units_14=1
  83 CSET match_units_15=1
  84 CSET match_units_16=1
  85 CSET match_units_2=1
  86 CSET match_units_3=1
  87 CSET match_units_4=1
  88 CSET match_units_5=1
  89 CSET match_units_6=1
  90 CSET match_units_7=1
  91 CSET match_units_8=1
  92 CSET match_units_9=1
  93 CSET max_sequence_levels=1
  94 CSET number_of_trigger_ports=1
  95 CSET sample_data_depth=4096
  96 CSET sample_on=Rising
  97 CSET trigger_port_width_1=32
  98 CSET trigger_port_width_10=8
  99 CSET trigger_port_width_11=8
 100 CSET trigger_port_width_12=8
 101 CSET trigger_port_width_13=8
 102 CSET trigger_port_width_14=8
 103 CSET trigger_port_width_15=8
 104 CSET trigger_port_width_16=8
 105 CSET trigger_port_width_2=8
 106 CSET trigger_port_width_3=8
 107 CSET trigger_port_width_4=8
 108 CSET trigger_port_width_5=8
 109 CSET trigger_port_width_6=8
 110 CSET trigger_port_width_7=8
 111 CSET trigger_port_width_8=8
 112 CSET trigger_port_width_9=8
 113 CSET use_rpms=true
 114 # END Parameters
 115 GENERATE