git.zerfleddert.de Git - raggedstone/blob - xps/data/raggedstone.ucf

   1 ############################################################################
   2 ## This system.ucf file is generated by Base System Builder based on the
   3 ## settings in the selected Xilinx Board Definition file. Please add other
   4 ## user constraints to this file based on customer design specifications.
   5 ############################################################################
   6
   7 Net sys_clk_pin LOC=AA11 | IOSTANDARD = LVCMOS33;
   8 Net sys_rst_pin LOC=AA3 | IOSTANDARD = LVCMOS33 | PULLUP;
   9 ## System level constraints
  10 Net sys_clk_pin TNM_NET = sys_clk_pin;
  11 TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;
  12 Net sys_rst_pin TIG;
  13
  14 ## IO Devices constraints
  15
  16 #### Module RS232 constraints
  17
  18 Net fpga_0_RS232_req_to_send_pin LOC=N20;
  19 Net fpga_0_RS232_req_to_send_pin IOSTANDARD = LVCMOS33;
  20 Net fpga_0_RS232_RX_pin LOC=Y22;
  21 Net fpga_0_RS232_RX_pin IOSTANDARD = LVCMOS33;
  22 Net fpga_0_RS232_TX_pin LOC=R18;
  23 Net fpga_0_RS232_TX_pin IOSTANDARD = LVCMOS33;
  24
  25 Net RS232foff LOC=T22 | IOSTANDARD = LVCMOS33;
  26
  27 #Net LED_out<0> LOC=AB5 | IOSTANDARD = LVTTL;
  28 Net LED_out<1> LOC=AA5 | IOSTANDARD = LVTTL;
  29 Net LED_out<2> LOC=AA4 | IOSTANDARD = LVTTL;
  30 Net LED_out<3> LOC=AB4 | IOSTANDARD = LVTTL;
  31
  32 Net SEVENSEG_out<12> LOC=AB20 | IOSTANDARD = LVTTL;
  33 Net SEVENSEG_out<11> LOC=AA20 | IOSTANDARD = LVTTL;
  34 Net SEVENSEG_out<10> LOC=V18 | IOSTANDARD = LVTTL;
  35 Net SEVENSEG_out<9> LOC=Y17 | IOSTANDARD = LVTTL;
  36 Net SEVENSEG_out<8> LOC=AB18 | IOSTANDARD = LVTTL;
  37 Net SEVENSEG_out<7> LOC=AA18 | IOSTANDARD = LVTTL;
  38 Net SEVENSEG_out<6> LOC=W18 | IOSTANDARD = LVTTL;
  39 Net SEVENSEG_out<5> LOC=W17 | IOSTANDARD = LVTTL;
  40 Net SEVENSEG_out<4> LOC=AA17 | IOSTANDARD = LVTTL;
  41 Net SEVENSEG_out<3> LOC=U17 | IOSTANDARD = LVTTL;
  42 Net SEVENSEG_out<2> LOC=U16 | IOSTANDARD = LVTTL;
  43 Net SEVENSEG_out<1> LOC=U14 | IOSTANDARD = LVTTL;
  44 Net SEVENSEG_out<0> LOC=V17 | IOSTANDARD = LVTTL;
  45
  46 Net MEM_FLASH_DQ<0> LOC=AA10 | IOSTANDARD = LVCMOS33;
  47 Net MEM_FLASH_DQ<1> LOC=W11 | IOSTANDARD = LVCMOS33;
  48 Net MEM_FLASH_DQ<2> LOC=Y11 | IOSTANDARD = LVCMOS33;
  49 Net MEM_FLASH_DQ<3> LOC=U11 | IOSTANDARD = LVCMOS33;
  50 Net MEM_FLASH_DQ<4> LOC=W13 | IOSTANDARD = LVCMOS33;
  51 Net MEM_FLASH_DQ<5> LOC=V13 | IOSTANDARD = LVCMOS33;
  52 Net MEM_FLASH_DQ<6> LOC=Y13 | IOSTANDARD = LVCMOS33;
  53 Net MEM_FLASH_DQ<7> LOC=W14 | IOSTANDARD = LVCMOS33;
  54
  55 Net MEM_FLASH_ADDR<0> LOC=Y10 | IOSTANDARD = LVCMOS33;
  56 Net MEM_FLASH_ADDR<1> LOC=W10 | IOSTANDARD = LVCMOS33;
  57 Net MEM_FLASH_ADDR<2> LOC=V10 | IOSTANDARD = LVCMOS33;
  58 Net MEM_FLASH_ADDR<3> LOC=W9 | IOSTANDARD = LVCMOS33;
  59 Net MEM_FLASH_ADDR<4> LOC=W8 | IOSTANDARD = LVCMOS33;
  60 Net MEM_FLASH_ADDR<5> LOC=AB8 | IOSTANDARD = LVCMOS33;
  61 Net MEM_FLASH_ADDR<6> LOC=AA8 | IOSTANDARD = LVCMOS33;
  62 Net MEM_FLASH_ADDR<7> LOC=AA9 | IOSTANDARD = LVCMOS33;
  63 Net MEM_FLASH_ADDR<8> LOC=V9 | IOSTANDARD = LVCMOS33;
  64 Net MEM_FLASH_ADDR<9> LOC=AA15 | IOSTANDARD = LVCMOS33;
  65 Net MEM_FLASH_ADDR<10> LOC=U12 | IOSTANDARD = LVCMOS33;
  66 Net MEM_FLASH_ADDR<11> LOC=AB15 | IOSTANDARD = LVCMOS33;
  67 Net MEM_FLASH_ADDR<12> LOC=AB9 | IOSTANDARD = LVCMOS33;
  68 Net MEM_FLASH_ADDR<13> LOC=AB14 | IOSTANDARD = LVCMOS33;
  69 Net MEM_FLASH_ADDR<14> LOC=AA13 | IOSTANDARD = LVCMOS33;
  70 Net MEM_FLASH_ADDR<15> LOC=AB10 | IOSTANDARD = LVCMOS33;
  71 Net MEM_FLASH_ADDR<16> LOC=AB11 | IOSTANDARD = LVCMOS33;
  72 Net MEM_FLASH_ADDR<17> LOC=AB13 | IOSTANDARD = LVCMOS33;
  73 Net MEM_FLASH_ADDR<18> LOC=Y12 | IOSTANDARD = LVCMOS33;
  74
  75 Net DBG_FLASH_ADDR<31> LOC=Y1 | IOSTANDARD = LVCMOS33;
  76 Net DBG_FLASH_ADDR<30> LOC=U2 | IOSTANDARD = LVCMOS33;
  77 Net DBG_FLASH_ADDR<29> LOC=U3 | IOSTANDARD = LVCMOS33;
  78 Net DBG_FLASH_ADDR<28> LOC=T1 | IOSTANDARD = LVCMOS33;
  79 Net DBG_FLASH_ADDR<27> LOC=T2 | IOSTANDARD = LVCMOS33;
  80 Net DBG_FLASH_ADDR<26> LOC=M6 | IOSTANDARD = LVCMOS33;
  81 Net DBG_FLASH_ADDR<25> LOC=M5 | IOSTANDARD = LVCMOS33;
  82 Net DBG_FLASH_ADDR<24> LOC=M1 | IOSTANDARD = LVCMOS33;
  83 Net DBG_FLASH_ADDR<23> LOC=M2 | IOSTANDARD = LVCMOS33;
  84 Net DBG_FLASH_ADDR<22> LOC=L5 | IOSTANDARD = LVCMOS33;
  85 Net DBG_FLASH_ADDR<21> LOC=L6 | IOSTANDARD = LVCMOS33;
  86 Net DBG_FLASH_ADDR<20> LOC=K1 | IOSTANDARD = LVCMOS33;
  87 Net DBG_FLASH_ADDR<19> LOC=K2 | IOSTANDARD = LVCMOS33;
  88 Net DBG_FLASH_ADDR<18> LOC=F4 | IOSTANDARD = LVCMOS33;
  89 Net DBG_FLASH_ADDR<17> LOC=E3 | IOSTANDARD = LVCMOS33;
  90 Net DBG_FLASH_ADDR<16> LOC=F2 | IOSTANDARD = LVCMOS33;
  91 Net DBG_FLASH_ADDR<15> LOC=F3 | IOSTANDARD = LVCMOS33;
  92 Net DBG_FLASH_ADDR<14> LOC=E2 | IOSTANDARD = LVCMOS33;
  93 Net DBG_FLASH_ADDR<13> LOC=E1 | IOSTANDARD = LVCMOS33;
  94 Net DBG_FLASH_ADDR<12> LOC=W1 | IOSTANDARD = LVCMOS33;
  95 Net DBG_FLASH_ADDR<11> LOC=W2 | IOSTANDARD = LVCMOS33;
  96 Net DBG_FLASH_ADDR<10> LOC=V5 | IOSTANDARD = LVCMOS33;
  97 Net DBG_FLASH_ADDR<9> LOC=U5 | IOSTANDARD = LVCMOS33;
  98 Net DBG_FLASH_ADDR<8> LOC=V2 | IOSTANDARD = LVCMOS33;
  99 Net DBG_FLASH_ADDR<7> LOC=V1 | IOSTANDARD = LVCMOS33;
 100 Net DBG_FLASH_ADDR<6> LOC=U4 | IOSTANDARD = LVCMOS33;
 101 Net DBG_FLASH_ADDR<5> LOC=T4 | IOSTANDARD = LVCMOS33;
 102 Net DBG_FLASH_ADDR<4> LOC=T5 | IOSTANDARD = LVCMOS33;
 103 Net DBG_FLASH_ADDR<3> LOC=T6 | IOSTANDARD = LVCMOS33;
 104 Net DBG_FLASH_ADDR<2> LOC=M4 | IOSTANDARD = LVCMOS33;
 105 Net DBG_FLASH_ADDR<1> LOC=M3 | IOSTANDARD = LVCMOS33;
 106 Net DBG_FLASH_ADDR<0> LOC=L3 | IOSTANDARD = LVCMOS33;
 107
 108 Net MEM_FLASH_CE<0> LOC=V14 | IOSTANDARD = LVCMOS33;
 109 Net MEM_FLASH_OE<0> LOC=U13 | IOSTANDARD = LVCMOS33;
 110 Net MEM_FLASH_WE LOC=W12 | IOSTANDARD = LVCMOS33;