1 //////////////////////////////////////////////////////////////////////
3 //// eth_macstatus.v ////
5 //// This file is part of the Ethernet IP core project ////
6 //// http://www.opencores.org/projects/ethmac/ ////
9 //// - Igor Mohor (igorM@opencores.org) ////
11 //// All additional information is available in the Readme.txt ////
14 //////////////////////////////////////////////////////////////////////
16 //// Copyright (C) 2001, 2002 Authors ////
18 //// This source file may be used and distributed without ////
19 //// restriction provided that this copyright statement is not ////
20 //// removed from the file and that any derivative work contains ////
21 //// the original copyright notice and the associated disclaimer. ////
23 //// This source file is free software; you can redistribute it ////
24 //// and/or modify it under the terms of the GNU Lesser General ////
25 //// Public License as published by the Free Software Foundation; ////
26 //// either version 2.1 of the License, or (at your option) any ////
27 //// later version. ////
29 //// This source is distributed in the hope that it will be ////
30 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
31 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
32 //// PURPOSE. See the GNU Lesser General Public License for more ////
35 //// You should have received a copy of the GNU Lesser General ////
36 //// Public License along with this source; if not, download it ////
37 //// from http://www.opencores.org/lgpl.shtml ////
39 //////////////////////////////////////////////////////////////////////
41 // CVS Revision History
43 // $Log: eth_macstatus.v,v $
44 // Revision 1.1 2007-03-20 17:50:56 sithglan
47 // Revision 1.17 2005/03/21 20:07:18 igorm
48 // Some small fixes + some troubles fixed.
50 // Revision 1.16 2005/02/21 10:42:11 igorm
51 // Defer indication fixed.
53 // Revision 1.15 2003/01/30 13:28:19 tadejm
54 // Defer indication changed.
56 // Revision 1.14 2002/11/22 01:57:06 mohor
57 // Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
60 // Revision 1.13 2002/11/13 22:30:58 tadejm
61 // Late collision is reported only when not in the full duplex.
62 // Sample is taken (for status) as soon as MRxDV is not valid (regardless
63 // of the received byte cnt).
65 // Revision 1.12 2002/09/12 14:50:16 mohor
66 // CarrierSenseLost bug fixed when operating in full duplex mode.
68 // Revision 1.11 2002/09/04 18:38:03 mohor
69 // CarrierSenseLost status is not set when working in loopback mode.
71 // Revision 1.10 2002/07/25 18:17:46 mohor
72 // InvalidSymbol generation changed.
74 // Revision 1.9 2002/04/22 13:51:44 mohor
75 // Short frame and ReceivedLengthOK were not detected correctly.
77 // Revision 1.8 2002/02/18 10:40:17 mohor
80 // Revision 1.7 2002/02/15 17:07:39 mohor
81 // Status was not written correctly when frames were discarted because of
84 // Revision 1.6 2002/02/11 09:18:21 mohor
85 // Tx status is written back to the BD.
87 // Revision 1.5 2002/02/08 16:21:54 mohor
88 // Rx status is written back to the BD.
90 // Revision 1.4 2002/01/23 10:28:16 mohor
91 // Link in the header changed.
93 // Revision 1.3 2001/10/19 08:43:51 mohor
94 // eth_timescale.v changed to timescale.v This is done because of the
95 // simulation of the few cores in a one joined project.
97 // Revision 1.2 2001/09/11 14:17:00 mohor
98 // Few little NCSIM warnings fixed.
100 // Revision 1.1 2001/08/06 14:44:29 mohor
101 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
102 // Include files fixed to contain no path.
103 // File names and module names changed ta have a eth_ prologue in the name.
104 // File eth_timescale.v is used to define timescale
105 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
106 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
107 // and Mdo_OE. The bidirectional signal must be created on the top level. This
108 // is done due to the ASIC tools.
110 // Revision 1.1 2001/07/30 21:23:42 mohor
111 // Directory structure changed. Files checked and joind together.
118 `include "timescale.v"
121 module eth_macstatus(
122 MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
123 MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
124 RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
125 InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
126 r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
127 LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
128 RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm,
129 StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
145 input [1:0] RxStateData;
146 input RxStatePreamble;
149 input [15:0] RxByteCnt;
151 input RxByteCntGreat2;
152 input RxByteCntMaxFrame;
155 input [5:0] CollValid;
157 input [15:0] r_MinFL;
158 input [15:0] r_MaxFL;
162 input [3:0] RetryCnt;
164 input MaxCollisionOccured;
166 input DeferIndication;
169 input [1:0] StateData;
176 output ReceivedLengthOK;
178 output ReceivedPacketGood;
179 output InvalidSymbol;
180 output LatchedCrcError;
181 output RxLateCollision;
183 output DribbleNibble;
184 output ReceivedPacketTooBig;
186 output [3:0] RetryCntLatched;
188 output LateCollLatched;
190 input RstDeferLatched;
191 output CarrierSenseLost;
192 output LatchedMRxErr;
201 reg [3:0] RetryCntLatched;
205 reg CarrierSenseLost;
208 wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
211 always @ (posedge MRxClk or posedge Reset)
214 LatchedCrcError <=#Tp 1'b0;
217 LatchedCrcError <=#Tp 1'b0;
220 LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
225 always @ (posedge MRxClk or posedge Reset)
228 LatchedMRxErr <=#Tp 1'b0;
230 if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
231 LatchedMRxErr <=#Tp 1'b1;
233 LatchedMRxErr <=#Tp 1'b0;
237 // ReceivedPacketGood
238 assign ReceivedPacketGood = ~LatchedCrcError;
242 assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
248 // Time to take a sample
249 //assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
250 assign TakeSample = (|RxStateData) & (~MRxDV) |
251 RxStateData[0] & MRxDV & RxByteCntMaxFrame;
255 always @ (posedge MRxClk or posedge Reset)
258 LoadRxStatus <=#Tp 1'b0;
260 LoadRxStatus <=#Tp TakeSample;
266 always @ (posedge MRxClk or posedge Reset)
269 ReceiveEnd <=#Tp 1'b0;
271 ReceiveEnd <=#Tp LoadRxStatus;
275 // Invalid Symbol received during 100Mbps mode
276 assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
280 always @ (posedge MRxClk or posedge Reset)
283 InvalidSymbol <=#Tp 1'b0;
285 if(LoadRxStatus & ~SetInvalidSymbol)
286 InvalidSymbol <=#Tp 1'b0;
289 InvalidSymbol <=#Tp 1'b1;
298 always @ (posedge MRxClk or posedge Reset)
301 RxLateCollision <=#Tp 1'b0;
304 RxLateCollision <=#Tp 1'b0;
306 if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
307 RxLateCollision <=#Tp 1'b1;
311 always @ (posedge MRxClk or posedge Reset)
314 RxColWindow <=#Tp 1'b1;
316 if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
317 RxColWindow <=#Tp 1'b0;
320 RxColWindow <=#Tp 1'b1;
326 always @ (posedge MRxClk or posedge Reset)
329 ShortFrame <=#Tp 1'b0;
332 ShortFrame <=#Tp 1'b0;
335 ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];
341 always @ (posedge MRxClk or posedge Reset)
344 DribbleNibble <=#Tp 1'b0;
347 DribbleNibble <=#Tp 1'b0;
349 if(~MRxDV & RxStateData[1])
350 DribbleNibble <=#Tp 1'b1;
354 reg ReceivedPacketTooBig;
355 always @ (posedge MRxClk or posedge Reset)
358 ReceivedPacketTooBig <=#Tp 1'b0;
361 ReceivedPacketTooBig <=#Tp 1'b0;
364 ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
369 // Latched Retry counter for tx status
370 always @ (posedge MTxClk or posedge Reset)
373 RetryCntLatched <=#Tp 4'h0;
375 if(StartTxDone | StartTxAbort)
376 RetryCntLatched <=#Tp RetryCnt;
380 // Latched Retransmission limit
381 always @ (posedge MTxClk or posedge Reset)
384 RetryLimit <=#Tp 1'h0;
386 if(StartTxDone | StartTxAbort)
387 RetryLimit <=#Tp MaxCollisionOccured;
391 // Latched Late Collision
392 always @ (posedge MTxClk or posedge Reset)
395 LateCollLatched <=#Tp 1'b0;
397 if(StartTxDone | StartTxAbort)
398 LateCollLatched <=#Tp LateCollision;
403 // Latched Defer state
404 always @ (posedge MTxClk or posedge Reset)
407 DeferLatched <=#Tp 1'b0;
410 DeferLatched <=#Tp 1'b1;
413 DeferLatched <=#Tp 1'b0;
418 always @ (posedge MTxClk or posedge Reset)
421 CarrierSenseLost <=#Tp 1'b0;
423 if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
424 CarrierSenseLost <=#Tp 1'b1;
427 CarrierSenseLost <=#Tp 1'b0;