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   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  eth_rxcounters.v                                            ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects/ethmac/                   ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Igor Mohor (igorM@opencores.org)                      ////
  10 ////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
  11 ////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
  12 ////                                                              ////
  13 ////  All additional information is avaliable in the Readme.txt   ////
  14 ////  file.                                                       ////
  15 ////                                                              ////
  16 //////////////////////////////////////////////////////////////////////
  17 ////                                                              ////
  18 //// Copyright (C) 2001 Authors                                   ////
  19 ////                                                              ////
  20 //// This source file may be used and distributed without         ////
  21 //// restriction provided that this copyright statement is not    ////
  22 //// removed from the file and that any derivative work contains  ////
  23 //// the original copyright notice and the associated disclaimer. ////
  24 ////                                                              ////
  25 //// This source file is free software; you can redistribute it   ////
  26 //// and/or modify it under the terms of the GNU Lesser General   ////
  27 //// Public License as published by the Free Software Foundation; ////
  28 //// either version 2.1 of the License, or (at your option) any   ////
  29 //// later version.                                               ////
  30 ////                                                              ////
  31 //// This source is distributed in the hope that it will be       ////
  32 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  33 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  34 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  35 //// details.                                                     ////
  36 ////                                                              ////
  37 //// You should have received a copy of the GNU Lesser General    ////
  38 //// Public License along with this source; if not, download it   ////
  39 //// from http://www.opencores.org/lgpl.shtml                     ////
  40 ////                                                              ////
  41 //////////////////////////////////////////////////////////////////////
  42 //
  43 // CVS Revision History
  44 //
  45 // $Log: eth_rxcounters.v,v $
  46 // Revision 1.1  2007-03-20 17:50:56  sithglan
  47 // add shit
  48 //
  49 // Revision 1.6  2005/02/21 11:00:57  igorm
  50 // Delayed CRC fixed.
  51 //
  52 // Revision 1.5  2002/02/15 11:13:29  mohor
  53 // Format of the file changed a bit.
  54 //
  55 // Revision 1.4  2002/02/14 20:19:41  billditt
  56 // Modified for Address Checking,
  57 // addition of eth_addrcheck.v
  58 //
  59 // Revision 1.3  2002/01/23 10:28:16  mohor
  60 // Link in the header changed.
  61 //
  62 // Revision 1.2  2001/10/19 08:43:51  mohor
  63 // eth_timescale.v changed to timescale.v This is done because of the
  64 // simulation of the few cores in a one joined project.
  65 //
  66 // Revision 1.1  2001/08/06 14:44:29  mohor
  67 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
  68 // Include files fixed to contain no path.
  69 // File names and module names changed ta have a eth_ prologue in the name.
  70 // File eth_timescale.v is used to define timescale
  71 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
  72 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
  73 // and Mdo_OE. The bidirectional signal must be created on the top level. This
  74 // is done due to the ASIC tools.
  75 //
  76 // Revision 1.1  2001/07/30 21:23:42  mohor
  77 // Directory structure changed. Files checked and joind together.
  78 //
  79 // Revision 1.1  2001/06/27 21:26:19  mohor
  80 // Initial release of the RxEthMAC module.
  81 //
  82 //
  83 //
  84 //
  85 //
  86 //
  87
  88
  89 `include "timescale.v"
  90
  91
  92 module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
  93                        MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
  94                        ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
  95                        ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
  96                       );
  97
  98 parameter Tp = 1;
  99
 100 input         MRxClk;
 101 input         Reset;
 102 input         MRxDV;
 103 input         StateSFD;
 104 input [1:0]   StateData;
 105 input         MRxDEqD;
 106 input         StateIdle;
 107 input         StateDrop;
 108 input         DlyCrcEn;
 109 input         StatePreamble;
 110 input         Transmitting;
 111 input         HugEn;
 112 input [15:0]  MaxFL;
 113 input         r_IFG;
 114
 115 output        IFGCounterEq24;           // IFG counter reaches 9600 ns (960 ns)
 116 output [3:0]  DlyCrcCnt;                // Delayed CRC counter
 117 output        ByteCntEq0;               // Byte counter = 0
 118 output        ByteCntEq1;               // Byte counter = 1
 119 output        ByteCntEq2;               // Byte counter = 2
 120 output        ByteCntEq3;               // Byte counter = 3
 121 output        ByteCntEq4;               // Byte counter = 4
 122 output        ByteCntEq5;               // Byte counter = 5
 123 output        ByteCntEq6;               // Byte counter = 6
 124 output        ByteCntEq7;               // Byte counter = 7
 125 output        ByteCntGreat2;            // Byte counter > 2
 126 output        ByteCntSmall7;            // Byte counter < 7
 127 output        ByteCntMaxFrame;          // Byte counter = MaxFL
 128 output [15:0] ByteCntOut;               // Byte counter
 129
 130 wire          ResetByteCounter;
 131 wire          IncrementByteCounter;
 132 wire          ResetIFGCounter;
 133 wire          IncrementIFGCounter;
 134 wire          ByteCntMax;
 135
 136 reg   [15:0]  ByteCnt;
 137 reg   [3:0]   DlyCrcCnt;
 138 reg   [4:0]   IFGCounter;
 139
 140 wire  [15:0]  ByteCntDelayed;
 141
 142
 143
 144 assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
 145
 146 assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
 147                               (StatePreamble | StateSFD | StateIdle & ~Transmitting |
 148                                StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
 149                               );
 150
 151
 152 always @ (posedge MRxClk or posedge Reset)
 153 begin
 154   if(Reset)
 155     ByteCnt[15:0] <= #Tp 16'h0;
 156   else
 157     begin
 158       if(ResetByteCounter)
 159         ByteCnt[15:0] <= #Tp 16'h0;
 160       else
 161       if(IncrementByteCounter)
 162         ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
 163      end
 164 end
 165
 166 assign ByteCntDelayed = ByteCnt + 3'h4;
 167 assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
 168
 169 assign ByteCntEq0       = ByteCnt == 16'h0;
 170 assign ByteCntEq1       = ByteCnt == 16'h1;
 171 assign ByteCntEq2       = ByteCnt == 16'h2;
 172 assign ByteCntEq3       = ByteCnt == 16'h3;
 173 assign ByteCntEq4       = ByteCnt == 16'h4;
 174 assign ByteCntEq5       = ByteCnt == 16'h5;
 175 assign ByteCntEq6       = ByteCnt == 16'h6;
 176 assign ByteCntEq7       = ByteCnt == 16'h7;
 177 assign ByteCntGreat2    = ByteCnt >  16'h2;
 178 assign ByteCntSmall7    = ByteCnt <  16'h7;
 179 assign ByteCntMax       = ByteCnt == 16'hffff;
 180 assign ByteCntMaxFrame  = ByteCnt == MaxFL[15:0] & ~HugEn;
 181
 182
 183 assign ResetIFGCounter = StateSFD  &  MRxDV & MRxDEqD | StateDrop;
 184
 185 assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
 186
 187 always @ (posedge MRxClk or posedge Reset)
 188 begin
 189   if(Reset)
 190     IFGCounter[4:0] <= #Tp 5'h0;
 191   else
 192     begin
 193       if(ResetIFGCounter)
 194         IFGCounter[4:0] <= #Tp 5'h0;
 195       else
 196       if(IncrementIFGCounter)
 197         IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1;
 198     end
 199 end
 200
 201
 202
 203 assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
 204
 205
 206 always @ (posedge MRxClk or posedge Reset)
 207 begin
 208   if(Reset)
 209     DlyCrcCnt[3:0] <= #Tp 4'h0;
 210   else
 211     begin
 212       if(DlyCrcCnt[3:0] == 4'h9)
 213         DlyCrcCnt[3:0] <= #Tp 4'h0;
 214       else
 215       if(DlyCrcEn & StateSFD)
 216         DlyCrcCnt[3:0] <= #Tp 4'h1;
 217       else
 218       if(DlyCrcEn & (|DlyCrcCnt[3:0]))
 219         DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1;
 220     end
 221 end
 222
 223
 224 endmodule