git.zerfleddert.de Git - raggedstone/blob - dhwk/source/pci/config_space_header.vhd

   1 -- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007
   2
   3 LIBRARY ieee;
   4
   5 USE ieee.std_logic_1164.ALL;
   6 USE ieee.numeric_std.ALL;
   7
   8
   9 entity CONFIG_SPACE_HEADER is
  10         Port ( AD_REG : In std_logic_vector (31 downto 0);
  11                ADDR_REG : In std_logic_vector (31 downto 0);
  12                CBE_REGn : In std_logic_vector (3 downto 0);
  13                CF_RD_COM : In std_logic;
  14                CF_WR_COM : In std_logic;
  15                IRDY_REGn : In std_logic;
  16                PCI_CLOCK : In std_logic;
  17                PCI_RSTn : In std_logic;
  18                PERR : In std_logic;
  19                REVISION_ID : In std_logic_vector (7 downto 0);
  20                SERR : In std_logic;
  21                TRDYn : In std_logic;
  22                VENDOR_ID : In std_logic_vector (15 downto 0);
  23                CONF_DATA : Out std_logic_vector (31 downto 0);
  24                CONF_DATA_04H : Out std_logic_vector (31 downto 0);
  25                CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
  26 end CONFIG_SPACE_HEADER;
  27
  28 architecture SCHEMATIC of CONFIG_SPACE_HEADER is
  29
  30         constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";
  31         --other comm. device
  32         constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";
  33
  34         signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
  35         signal CONF_MIN_GNT :std_logic_vector (23 downto 16);
  36         signal CONF_INT_PIN :std_logic_vector (15 downto 8);
  37         signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);
  38
  39         signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0);
  40
  41         signal CONF_STATUS :std_logic_vector(31 downto 16);
  42         signal CONF_COMMAND :std_logic_vector(15 downto 0);
  43
  44         SIGNAL gnd : std_logic := '0';
  45         SIGNAL vcc : std_logic := '1';
  46
  47         signal CONF_WR_04H : std_logic;
  48         signal CONF_WR_10H : std_logic;
  49         signal CONF_WR_3CH : std_logic;
  50         signal CONF_READ_SEL : std_logic_vector (2 downto 0);
  51         signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
  52         signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
  53         signal CONF_DATA_08H : std_logic_vector (31 downto 0);
  54         signal CONF_DATA_00H : std_logic_vector (31 downto 0);
  55
  56         component CONFIG_RD_0
  57                 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
  58                        CF_RD_COM : In std_logic;
  59                        READ_SEL : Out std_logic_vector (2 downto 0) );
  60         end component;
  61
  62         component CONFIG_WR_0
  63                 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
  64                        CF_WR_COM : In std_logic;
  65                        IRDY_REGn : In std_logic;
  66                        TRDYn : In std_logic;
  67                        CONF_WR_04H : Out std_logic;
  68                        CONF_WR_10H : Out std_logic;
  69                        CONF_WR_3CH : Out std_logic );
  70         end component;
  71
  72 begin
  73         CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
  74         CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
  75         CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND;
  76
  77         CONF_MAX_LAT <= X"00";
  78         CONF_MIN_GNT <= X"00";
  79         -- CONF_INT_PIN <= X"00"; -- Interrupt -
  80         CONF_INT_PIN <= X"01"; -- Interrupt A
  81         -- CONF_INT_PIN <= X"02"; -- Interrupt B
  82         -- CONF_INT_PIN <= X"03"; -- Interrupt C
  83         -- CONF_INT_PIN <= X"04"; -- Interrupt D
  84         -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
  85         CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
  86
  87         CONF_BAS_ADDR_REG(1 downto 0) <= "01";-- Base Address Register for "I/O"
  88         CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE
  89         CONF_DATA_10H <= CONF_BAS_ADDR_REG;
  90
  91         I9 : CONFIG_RD_0
  92         Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
  93                    CF_RD_COM=>CF_RD_COM,
  94                    READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
  95         I8 : CONFIG_WR_0
  96         Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
  97                    CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
  98                    TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
  99                    CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
 100
 101         process (PCI_CLOCK,PCI_RSTn)
 102         begin
 103         if PCI_RSTn = '0' then
 104                 CONF_INT_LINE <= (others => '0');
 105
 106         elsif (rising_edge(PCI_CLOCK)) then
 107                 if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
 108                         CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
 109                 end if;
 110         end if;
 111         end process;
 112
 113         process (PCI_CLOCK,PCI_RSTn)
 114         begin
 115
 116         -- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
 117         if PCI_RSTn = '0' then
 118                 CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
 119
 120         elsif (rising_edge(PCI_CLOCK)) then
 121
 122                 if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then
 123                         CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
 124                 else
 125                         CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
 126                 end if;
 127
 128                 if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then
 129                         CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
 130                 else
 131                         CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
 132                 end if;
 133
 134                 if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then
 135                         CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8);
 136                 else
 137                         CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8);
 138                 end if;
 139
 140                 -- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
 141                 --         CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2);
 142                 -- else
 143                 --         CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2);
 144                 -- end if;
 145
 146                 if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
 147                         CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4);
 148                 else
 149                         CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4);
 150                 end if;
 151         end if;
 152         end process;
 153
 154         --*******************************************************************
 155         --************* PCI Configuration Space Header "STATUS" *************
 156         --*******************************************************************
 157
 158         CONF_STATUS(20 downto 16) <= "00000";-- Reserved
 159         CONF_STATUS(21 ) <= '0';-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz
 160         CONF_STATUS(22 ) <= '0';-- MAS/TAR: "R_O"
 161         CONF_STATUS(23 ) <= '0';-- ???/???: "R_O" : fast back-to-back
 162         CONF_STATUS(24 ) <= '0';-- Master :
 163         --CONF_STATUS(26 downto 25) <= "00";-- Mas/Tar: "R_O" : timing fast for "DEVSEL"
 164         CONF_STATUS(26 downto 25) <= "01";-- Mas/Tar: "R_O" : timing medium for "DEVSEL"
 165         --CONF_STATUS(26 downto 25) <= "10";-- Mas/Tar: "R_O" : timing slow for "DEVSEL"
 166         --CONF_STATUS(26 downto 25) <= "11";-- Mas/Tar: "R_O" : reserved
 167         CONF_STATUS(27 ) <= '0';-- Target : "R_W" : Taget-Abort
 168         CONF_STATUS(28 ) <= '0';-- Master : "R_W" : Taget-Abort
 169         CONF_STATUS(29 ) <= '0';-- Master : "R_W" : Master-Abort
 170         --CONF_STATUS(30 ) <= SERR;-- Mas/Tar: "R_W" : SERR
 171         --CONF_STATUS(31 ) <= PERR;-- Mas/Tar: "R_W" : PERR
 172
 173         process (PCI_CLOCK,PCI_RSTn)
 174         begin
 175         if PCI_RSTn = '0' then
 176                 CONF_STATUS(30) <= '0';
 177                 CONF_STATUS(31) <= '0';
 178
 179         elsif (rising_edge(PCI_CLOCK)) then
 180                 if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then
 181                         CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30));
 182                         CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));
 183
 184                 else
 185                         CONF_STATUS(30) <= SERR or CONF_STATUS(30);
 186                         CONF_STATUS(31) <= PERR or CONF_STATUS(31);
 187
 188                 end if;
 189         end if;
 190         end process;
 191
 192         --*******************************************************************
 193         --*********** PCI Configuration Space Header "COMMAND" **************
 194         --*******************************************************************
 195
 196         -- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???
 197         -- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???
 198         -- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus
 199         -- CONF_COMMAND( 3) <= '0';-- Special Cycle ???
 200         -- CONF_COMMAND( 4) <= '0';-- Master ???
 201         -- CONF_COMMAND( 5) <= '0';-- VGA ???
 202         -- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable
 203         CONF_COMMAND( 7) <= '0';-- address/data stepping ???
 204         -- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"
 205         -- CONF_COMMAND( 9) <= '0';-- fast back-to-back
 206         -- CONF_COMMAND(10) <= '0';-- Reserved
 207         -- CONF_COMMAND(11) <= '0';-- Reserved
 208         -- CONF_COMMAND(12) <= '0';-- Reserved
 209         -- CONF_COMMAND(13) <= '0';-- Reserved
 210         -- CONF_COMMAND(14) <= '0';-- Reserved
 211         -- CONF_COMMAND(15) <= '0';-- Reserved
 212
 213         process (PCI_CLOCK,PCI_RSTn)
 214         begin
 215                 if PCI_RSTn = '0' then
 216                         CONF_COMMAND(15 downto 8) <= (others =>'0');
 217                         CONF_COMMAND( 6 downto 0) <= (others =>'0');
 218
 219                 elsif (rising_edge(PCI_CLOCK)) then
 220
 221                         if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then
 222                                 CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8);
 223                         else
 224                                 CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8);
 225                         end if;
 226
 227                         if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then
 228                                 CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0);
 229                         else
 230                                 CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0);
 231                         end if;
 232                 end if;
 233         end process;
 234 end SCHEMATIC;