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+= use xilinx block ram for ethernet
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1 //////////////////////////////////////////////////////////////////////
2 //// ////
3 //// TODO ////
4 //// ////
5 //// This file is part of the Ethernet IP core project ////
6 //// http://www.opencores.org/projects/ethmac/ ////
7 //// ////
8 //// Author(s): ////
9 //// - Igor Mohor (igorM@opencores.org) ////
10 //// ////
11 //// All additional information is available in the Readme.txt ////
12 //// file. ////
13 //// ////
14 //////////////////////////////////////////////////////////////////////
15 //// ////
16 //// Copyright (C) 2001, 2002 Authors ////
17 //// ////
18 //// This source file may be used and distributed without ////
19 //// restriction provided that this copyright statement is not ////
20 //// removed from the file and that any derivative work contains ////
21 //// the original copyright notice and the associated disclaimer. ////
22 //// ////
23 //// This source file is free software; you can redistribute it ////
24 //// and/or modify it under the terms of the GNU Lesser General ////
25 //// Public License as published by the Free Software Foundation; ////
26 //// either version 2.1 of the License, or (at your option) any ////
27 //// later version. ////
28 //// ////
29 //// This source is distributed in the hope that it will be ////
30 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
31 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
32 //// PURPOSE. See the GNU Lesser General Public License for more ////
33 //// details. ////
34 //// ////
35 //// You should have received a copy of the GNU Lesser General ////
36 //// Public License along with this source; if not, download it ////
37 //// from http://www.opencores.org/lgpl.shtml ////
38 //// ////
39 //////////////////////////////////////////////////////////////////////
40 //
41 // CVS Revision History
42 //
43 // $Log: TODO,v $
44 // Revision 1.1 2007-03-20 17:50:56 sithglan
45 // add shit
46 //
47 // Revision 1.3 2003/01/23 09:14:12 mohor
48 // Fix MTxErr or prevent sending too big frames.
49 //
50 // Revision 1.2 2002/11/21 00:33:32 mohor
51 // In loopback rx_clk is not looped back. Possible CRC error. Consider if usage
52 // of additional logic is necessery (FIFO for looping the data).
53 //
54 // Revision 1.1 2002/09/10 10:42:06 mohor
55 // HASH improvement needed.
56 //
57
58
59 - Add logic for easier use of the HASH table: First write MAC address to some
60 register. Then issue a command. CRC is calculated from this MAC and appropriate
61 bit written to the HASH register.
62
63 - In loopback rx_clk is not looped back. Possible CRC error. Consider if usage of
64 additional logic is necessery (FIFO for looping the data).
65
66 - When sending frames bigger than MaxFL, MaxFL is sent, BD marked as finished,
67 TxB_IRQ interrupt is set and MTxErr is set for a short period. Fix MTxErr or
68 prevent sending too big frames or set TxE_IRQ instead.
69
70
71
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