f0b7a515ba47f65871ded349cdf021f4d1ab9db8
[raggedstone] / dhwk / source / pci_top.vhd
1 -- VHDL model created from schematic pci_top.sch -- Jan 09 09:34:14 2007
2
3
4
5 LIBRARY ieee;
6
7 USE ieee.std_logic_1164.ALL;
8 USE ieee.numeric_std.ALL;
9
10
11 entity PCI_TOP is
12 Port ( FLAG : In std_logic_vector (7 downto 0);
13 INT_REG : In std_logic_vector (7 downto 0);
14 PCI_CBEn : In std_logic_vector (3 downto 0);
15 PCI_CLOCK : In std_logic;
16 PCI_FRAMEn : In std_logic;
17 PCI_IDSEL : In std_logic;
18 PCI_IRDYn : In std_logic;
19 PCI_RSTn : In std_logic;
20 R_FIFO_Q : In std_logic_vector (7 downto 0);
21 REVISON_ID : In std_logic_vector (7 downto 0);
22 VENDOR_ID : In std_logic_vector (15 downto 0);
23 PCI_AD : InOut std_logic_vector (31 downto 0);
24 PCI_PAR : InOut std_logic;
25 AD_REG : Out std_logic_vector (31 downto 0);
26 DEVSELn : Out std_logic;
27 FIFO_RDn : Out std_logic;
28 PCI_DEVSELn : Out std_logic;
29 PCI_PERRn : Out std_logic;
30 PCI_SERRn : Out std_logic;
31 PCI_STOPn : Out std_logic;
32 PCI_TRDYn : Out std_logic;
33 READ_SEL : Out std_logic_vector (1 downto 0);
34 READ_XX1_0 : Out std_logic;
35 READ_XX3_2 : Out std_logic;
36 READ_XX5_4 : Out std_logic;
37 READ_XX7_6 : Out std_logic;
38 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
39 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
40 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
41 TRDYn : Out std_logic;
42 WRITE_XX1_0 : Out std_logic;
43 WRITE_XX3_2 : Out std_logic;
44 WRITE_XX5_4 : Out std_logic;
45 WRITE_XX7_6 : Out std_logic );
46 end PCI_TOP;
47
48 architecture SCHEMATIC of PCI_TOP is
49
50 SIGNAL gnd : std_logic := '0';
51 SIGNAL vcc : std_logic := '1';
52
53 signal IRDY_REGn : std_logic;
54 signal IO_WR_COM : std_logic;
55 signal TRDYn_DUMMY : std_logic;
56 signal READ_XX3_2_DUMMY : std_logic;
57 signal USER_DATA_OUT : std_logic_vector (31 downto 0);
58 signal CBE_REGn : std_logic_vector (3 downto 0);
59 signal AD_REG_DUMMY : std_logic_vector (31 downto 0);
60 signal ADDR_REG : std_logic_vector (31 downto 0);
61 signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);
62
63 component USER_IO
64 Port ( AD_REG : In std_logic_vector (31 downto 0);
65 ADDR_REG : In std_logic_vector (31 downto 0);
66 CBE_REGn : In std_logic_vector (3 downto 0);
67 FLAG : In std_logic_vector (7 downto 0);
68 INT_REG : In std_logic_vector (7 downto 0);
69 IO_WR_COM : In std_logic;
70 IRDY_REGn : In std_logic;
71 PCI_CLK : In std_logic;
72 R_FIFO_Q : In std_logic_vector (7 downto 0);
73 READ_SEL : In std_logic_vector (1 downto 0);
74 TRDYn : In std_logic;
75 READ_XX1_0 : Out std_logic;
76 READ_XX3_2 : Out std_logic;
77 READ_XX5_4 : Out std_logic;
78 READ_XX7_6 : Out std_logic;
79 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
80 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
81 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
82 USER_DATA_OUT : Out std_logic_vector (31 downto 0);
83 WRITE_XX1_0 : Out std_logic;
84 WRITE_XX3_2 : Out std_logic;
85 WRITE_XX5_4 : Out std_logic;
86 WRITE_XX7_6 : Out std_logic );
87 end component;
88
89 component PCI_INTERFACE
90 Port ( PCI_CBEn : In std_logic_vector (3 downto 0);
91 PCI_CLOCK : In std_logic;
92 PCI_FRAMEn : In std_logic;
93 PCI_IDSEL : In std_logic;
94 PCI_IRDYn : In std_logic;
95 PCI_RSTn : In std_logic;
96 READ_FIFO : In std_logic;
97 REVISON_ID : In std_logic_vector (7 downto 0);
98 USER_DATA_OUT : In std_logic_vector (31 downto 0);
99 VENDOR_ID : In std_logic_vector (15 downto 0);
100 PCI_AD : InOut std_logic_vector (31 downto 0);
101 PCI_PAR : InOut std_logic;
102 AD_REG : Out std_logic_vector (31 downto 0);
103 ADDR_REG : Out std_logic_vector (31 downto 0);
104 CBE_REGn : Out std_logic_vector (3 downto 0);
105 DEVSELn : Out std_logic;
106 FIFO_RDn : Out std_logic;
107 IO_WR_COM : Out std_logic;
108 IRDY_REGn : Out std_logic;
109 PCI_DEVSELn : Out std_logic;
110 PCI_PERRn : Out std_logic;
111 PCI_SERRn : Out std_logic;
112 PCI_STOPn : Out std_logic;
113 PCI_TRDYn : Out std_logic;
114 READ_SEL : Out std_logic_vector (1 downto 0);
115 TRDYn : Out std_logic );
116 end component;
117
118 begin
119
120 READ_SEL <= READ_SEL_DUMMY;
121 AD_REG <= AD_REG_DUMMY;
122 READ_XX3_2 <= READ_XX3_2_DUMMY;
123 TRDYn <= TRDYn_DUMMY;
124
125 I19 : USER_IO
126 Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
127 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
128 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
129 FLAG(7 downto 0)=>FLAG(7 downto 0),
130 INT_REG(7 downto 0)=>INT_REG(7 downto 0),
131 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
132 PCI_CLK=>PCI_CLOCK,
133 R_FIFO_Q(7 downto 0)=>R_FIFO_Q(7 downto 0),
134 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
135 TRDYn=>TRDYn_DUMMY, READ_XX1_0=>READ_XX1_0,
136 READ_XX3_2=>READ_XX3_2_DUMMY, READ_XX5_4=>READ_XX5_4,
137 READ_XX7_6=>READ_XX7_6,
138 REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0(7 downto 0),
139 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
140 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
141 USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
142 WRITE_XX1_0=>WRITE_XX1_0, WRITE_XX3_2=>WRITE_XX3_2,
143 WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 );
144 I10 : PCI_INTERFACE
145 Port Map ( PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
146 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
147 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
148 PCI_RSTn=>PCI_RSTn, READ_FIFO=>READ_XX3_2_DUMMY,
149 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
150 USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
151 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
152 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
153 PCI_PAR=>PCI_PAR,
154 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),
155 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
156 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
157 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
158 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
159 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
160 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
161 PCI_TRDYn=>PCI_TRDYn,
162 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),
163 TRDYn=>TRDYn_DUMMY );
164
165 end SCHEMATIC;
Impressum, Datenschutz