git.zerfleddert.de Git - raggedstone/blob - xps/raggedstone.mhs

   1
   2 # ##############################################################################
   3 # Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
   4 # Thu Mar 22 21:42:23 2007
   5 # Target Board:  Custom
   6 # Family:        spartan3
   7 # Device:        xc3s1500
   8 # Package:       fg456
   9 # Speed Grade:   -4
  10 # Processor: Microblaze
  11 # System clock frequency: 50.000000 MHz
  12 # Debug interface: On-Chip HW Debug Module
  13 # On Chip Memory :  64 KB
  14 # ##############################################################################
  15  PARAMETER VERSION = 2.1.0
  16
  17
  18  PORT fpga_0_RS232_req_to_send_pin = net_gnd, DIR = O
  19  PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
  20  PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
  21  PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
  22  PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
  23  PORT RS232foff = net_vcc, DIR = O
  24  PORT MEM_FLASH_DQ = FLASH_DQ, DIR = IO, VEC = [7:0]
  25  PORT MEM_FLASH_ADDR = FLASH_ADDR, DIR = O, VEC = [18:0]
  26  PORT MEM_FLASH_CE = FLASH_CEN, DIR = O, VEC = [0:0]
  27  PORT MEM_FLASH_OE = FLASH_OEN, DIR = O, VEC = [0:0]
  28  PORT MEM_FLASH_WE = FLASH_WEN, DIR = O
  29  PORT SEVENSEG_out = GPIO_7SEG_OUT, DIR = O, VEC = [0:12]
  30  PORT DBG_FLASH_ADDR = FLASH_ADDR_split, DIR = O, VEC = [0:31]
  31  PORT LED_out = LEDS_GPIO_d_out, DIR = O, VEC = [0:3]
  32
  33
  34 BEGIN lmb_v10
  35  PARAMETER INSTANCE = ilmb
  36  PARAMETER HW_VER = 1.00.a
  37  PORT SYS_Rst = sys_bus_reset
  38  PORT LMB_Clk = sys_clk_s
  39 END
  40
  41 BEGIN lmb_v10
  42  PARAMETER INSTANCE = dlmb
  43  PARAMETER HW_VER = 1.00.a
  44  PORT SYS_Rst = sys_bus_reset
  45  PORT LMB_Clk = sys_clk_s
  46 END
  47
  48 BEGIN bram_block
  49  PARAMETER INSTANCE = lmb_bram
  50  PARAMETER HW_VER = 1.00.a
  51  BUS_INTERFACE PORTA = dlmb_cntlr_BRAM_PORT
  52  BUS_INTERFACE PORTB = ilmb_cntlr_BRAM_PORT
  53 END
  54
  55 BEGIN chipscope_icon
  56  PARAMETER INSTANCE = chipscope_icon_0
  57  PARAMETER HW_VER = 1.02.a
  58  PORT control0 = ila_control0
  59 END
  60
  61 BEGIN chipscope_ila
  62  PARAMETER INSTANCE = chipscope_ila_0
  63  PARAMETER HW_VER = 1.02.a
  64  PARAMETER C_NUM_DATA_SAMPLES = 1024
  65  PARAMETER C_TRIG0_TRIGGER_IN_WIDTH = 19
  66  PARAMETER C_ENABLE_TRIGGER_OUT = 0
  67  PARAMETER C_DISABLE_RPM = 1
  68  PORT CHIPSCOPE_ILA_CONTROL = ila_control0
  69  PORT CLK = sys_clk_s
  70  PORT TRIG0 = FLASH_ADDR
  71 END
  72
  73 BEGIN util_bus_split
  74  PARAMETER INSTANCE = flash_split
  75  PARAMETER HW_VER = 1.00.a
  76  PARAMETER C_SIZE_IN = 32
  77  PARAMETER C_SPLIT = 13
  78  PORT Sig = FLASH_ADDR_split
  79  PORT Out2 = FLASH_ADDR
  80 END
  81
  82 BEGIN microblaze
  83  PARAMETER INSTANCE = microblaze_0
  84  PARAMETER HW_VER = 7.10.b
  85  PARAMETER C_DEBUG_ENABLED = 1
  86  PARAMETER C_NUMBER_OF_PC_BRK = 2
  87  PARAMETER C_FAMILY = spartan3
  88  PARAMETER C_INSTANCE = microblaze_0
  89  PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 0
  90  PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 0
  91  BUS_INTERFACE DEBUG = mdm_0_MBDEBUG_0
  92  BUS_INTERFACE IPLB = mb_plb
  93  BUS_INTERFACE DPLB = mb_plb
  94  BUS_INTERFACE DLMB = dlmb
  95  BUS_INTERFACE ILMB = ilmb
  96  PORT MB_RESET = mb_reset
  97 END
  98
  99 BEGIN lmb_bram_if_cntlr
 100  PARAMETER INSTANCE = dlmb_cntlr
 101  PARAMETER HW_VER = 2.10.a
 102  PARAMETER C_BASEADDR = 0x00000000
 103  PARAMETER C_HIGHADDR = 0x00007fff
 104  BUS_INTERFACE SLMB = dlmb
 105  BUS_INTERFACE BRAM_PORT = dlmb_cntlr_BRAM_PORT
 106 END
 107
 108 BEGIN lmb_bram_if_cntlr
 109  PARAMETER INSTANCE = ilmb_cntlr
 110  PARAMETER HW_VER = 2.10.a
 111  PARAMETER C_BASEADDR = 0x00000000
 112  PARAMETER C_HIGHADDR = 0x00007fff
 113  BUS_INTERFACE SLMB = ilmb
 114  BUS_INTERFACE BRAM_PORT = ilmb_cntlr_BRAM_PORT
 115 END
 116
 117 BEGIN mdm
 118  PARAMETER INSTANCE = debug_module
 119  PARAMETER HW_VER = 1.00.b
 120  PARAMETER C_BASEADDR = 0x84400000
 121  PARAMETER C_HIGHADDR = 0x8440ffff
 122  PARAMETER C_MB_DBG_PORTS = 1
 123  BUS_INTERFACE MBDEBUG_0 = mdm_0_MBDEBUG_0
 124  BUS_INTERFACE SPLB = mb_plb
 125  PORT Debug_SYS_Rst = MB_Debug_Sys_Rst
 126 END
 127
 128 BEGIN plb_v46
 129  PARAMETER INSTANCE = mb_plb
 130  PARAMETER HW_VER = 1.02.a
 131  PORT SYS_Rst = sys_bus_reset
 132  PORT PLB_Clk = sys_clk_s
 133 END
 134
 135 BEGIN xps_gpio
 136  PARAMETER INSTANCE = LEDS
 137  PARAMETER HW_VER = 1.00.a
 138  PARAMETER C_GPIO_WIDTH = 4
 139  PARAMETER C_BASEADDR = 0x84418000
 140  PARAMETER C_HIGHADDR = 0x844181ff
 141  BUS_INTERFACE SPLB = mb_plb
 142  PORT GPIO_d_out = LEDS_GPIO_d_out
 143 END
 144
 145 BEGIN xps_uartlite
 146  PARAMETER INSTANCE = RS232
 147  PARAMETER HW_VER = 1.00.a
 148  PARAMETER C_BAUDRATE = 115200
 149  PARAMETER C_USE_PARITY = 0
 150  PARAMETER C_BASEADDR = 0x84000000
 151  PARAMETER C_HIGHADDR = 0x8400ffff
 152  PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
 153  BUS_INTERFACE SPLB = mb_plb
 154  PORT TX = fpga_0_RS232_TX
 155  PORT RX = fpga_0_RS232_RX
 156 END
 157
 158 BEGIN proc_sys_reset
 159  PARAMETER INSTANCE = proc_sys_reset_0
 160  PARAMETER HW_VER = 2.00.a
 161  PARAMETER C_EXT_RESET_HIGH = 0
 162  PORT MB_Debug_Sys_Rst = MB_Debug_Sys_Rst
 163  PORT Bus_Struct_Reset = sys_bus_reset
 164  PORT MB_Reset = mb_reset
 165  PORT Ext_Reset_In = sys_rst_s
 166  PORT Slowest_sync_clk = sys_clk_s
 167  PORT Dcm_locked = dcm_locked
 168 END
 169
 170 BEGIN xps_mch_emc
 171  PARAMETER INSTANCE = FLASH
 172  PARAMETER HW_VER = 1.01.a
 173  PARAMETER C_MEM0_BASEADDR = 0x20000000
 174  PARAMETER C_MEM0_HIGHADDR = 0x2007FFFF
 175  PARAMETER C_NUM_CHANNELS = 0
 176  PARAMETER C_MAX_MEM_WIDTH = 8
 177  PARAMETER C_MEM0_WIDTH = 8
 178  PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 179  PARAMETER C_TCEDV_PS_MEM_0 = 70000
 180  PARAMETER C_TAVDV_PS_MEM_0 = 70000
 181  PARAMETER C_THZCE_PS_MEM_0 = 25000
 182  PARAMETER C_THZOE_PS_MEM_0 = 25000
 183  PARAMETER C_TWC_PS_MEM_0 = 110000
 184  PARAMETER C_TWP_PS_MEM_0 = 70000
 185  PARAMETER C_TLZWE_PS_MEM_0 = 15000
 186  PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 20000
 187  BUS_INTERFACE SPLB = mb_plb
 188  PORT Mem_DQ = FLASH_DQ
 189  PORT Mem_WEN = FLASH_WEN
 190  PORT Mem_OEN = FLASH_OEN
 191  PORT Mem_CEN = FLASH_CEN
 192  PORT Mem_A = FLASH_ADDR_split
 193 END
 194
 195 BEGIN xps_gpio
 196  PARAMETER INSTANCE = SEVENSEG
 197  PARAMETER HW_VER = 1.00.a
 198  PARAMETER C_BASEADDR = 0x40000000
 199  PARAMETER C_HIGHADDR = 0x400001FF
 200  PARAMETER C_GPIO_WIDTH = 13
 201  BUS_INTERFACE SPLB = mb_plb
 202  PORT GPIO_d_out = GPIO_7SEG_OUT
 203 END
 204
 205 BEGIN clock_generator
 206  PARAMETER INSTANCE = clock_generator_0
 207  PARAMETER HW_VER = 2.01.a
 208  PARAMETER C_CLKIN_FREQ = 50000000
 209  PARAMETER C_EXT_RESET_HIGH = 1
 210  PARAMETER C_CLKOUT0_FREQ = 50000000
 211  PORT CLKIN = dcm_clk_s
 212  PORT RST = net_gnd
 213  PORT CLKOUT0 = sys_clk_s
 214  PORT LOCKED = dcm_locked
 215 END
 216