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2 //

3 // This source file is free software; you can redistribute it

4 // and/or modify it under the terms of the GNU Lesser General

5 // Public License as published by the Free Software Foundation;

6 // either version 2.1 of the License, or (at your option) any

7 // later version.

8 //

10 (* signal_encoding = "user" *)

11 (* safe_implementation = "yes" *)

13 module pciwbsequ_new ( clk_i, nrst_i, cmd_i, cbe_i, frame_i, irdy_i, devsel_o,

14 trdy_o, adrcfg_i, adrmem_i, pciadrLD_o, pcidOE_o, parOE_o, wbdatLD_o,

15 wbrgdMX_o, wbd16MX_o, wrcfg_o, rdcfg_o, wb_sel_o, wb_we_o, wb_stb_o,

16 wb_cyc_o, wb_ack_i, wb_err_i, debug_init, debug_access );

18 // General

19 input clk_i;

20 input nrst_i;

21 // pci

22 // adr_i

23 input [3:0] cmd_i;

24 input [3:0] cbe_i;

25 input frame_i;

26 input irdy_i;

27 output devsel_o;

28 output trdy_o;

29 // control

30 input adrcfg_i;

31 input adrmem_i;

32 output pciadrLD_o;

33 output pcidOE_o;

34 output reg parOE_o;

35 output wbdatLD_o;

36 output wbrgdMX_o;

37 output wbd16MX_o;

38 output wrcfg_o;

39 output rdcfg_o;

40 // whisbone

41 output [1:0] wb_sel_o;

42 output wb_we_o;

43 inout wb_stb_o;

44 output wb_cyc_o;

45 input wb_ack_i;

46 input wb_err_i;

47 // debug signals

48 output reg debug_init;

49 output reg debug_access;

51 //type PciFSM is ( PCIIDLE, B_BUSY, S_DATA1, S_DATA2, TURN_AR );

52 //wire pst_pci : PciFSM;

53 //wire nxt_pci : PciFSM;

55 // typedef enum reg [2:0] {

56 // RED, GREEN, BLUE, CYAN, MAGENTA, YELLOW

57 // } color_t;

58 //

59 // color_t my_color = GREEN;

61 // parameter PCIIDLE = 2'b00;

62 // parameter B_BUSY = 2'b01;

63 // parameter S_DATA1 = 2'b10;

64 // parameter S_DATA2 = 2'b11;

65 // parameter TURN_AR = 3'b100;

67 reg [2:0] pst_pci;

68 reg [2:0] nxt_pci;

70 parameter [2:0]

71 PCIIDLE = 3'b000,

72 B_BUSY = 3'b001,

73 S_DATA1 = 3'b010,

74 S_DATA2 = 3'b011,

75 TURN_AR = 3'b100;

78 initial begin

79 pst_pci = 3'b000;

80 end

82 initial begin

83 nxt_pci = 3'b000;

84 end

86 wire sdata1;

87 wire sdata2;

88 wire idleNX;

89 wire sdata1NX;

90 wire sdata2NX;

91 wire turnarNX;

92 wire idle;

93 reg devselNX_n;

94 reg trdyNX_n;

95 reg devsel;

96 reg trdy;

97 wire adrpci;

98 wire acking;

99 wire rdcfg;

100 reg targOE;

101 reg pcidOE;

102

103 // always @(nrst_i or clk_i or nxt_pci)

104 always @(negedge nrst_i or posedge clk_i)

105 begin

106 if( nrst_i == 0 )

107 pst_pci <= PCIIDLE;

108 else

109 pst_pci <= nxt_pci;

110 end

111

112 // always @(negedge nrst_i or posedge clk_i)

113 always @( pst_pci or frame_i or irdy_i or adrcfg_i or adrpci or acking )

114 begin

115 devselNX_n <= 1'b1;

116 trdyNX_n <= 1'b1;

117 case (pst_pci)

118 PCIIDLE :

119 begin

120 if ( frame_i == 0 )

121 nxt_pci <= B_BUSY;

122 else

123 nxt_pci <= PCIIDLE;

124 end

125 B_BUSY:

126 if ( adrpci == 0 )

127 nxt_pci <= TURN_AR;

128 else

129 begin

130 nxt_pci <= S_DATA1;

131 devselNX_n <= 0;

132 end

133 S_DATA1:

134 if ( acking == 1 )

135 begin

136 nxt_pci <= S_DATA2;

137 devselNX_n <= 0;

138 trdyNX_n <= 0;

139 end

140 else

141 begin

142 nxt_pci <= S_DATA1;

143 devselNX_n <= 0;

144 end

145 S_DATA2:

146 if ( frame_i == 1 && irdy_i == 0 )

147 nxt_pci <= TURN_AR;

148 else

149 begin

150 nxt_pci <= S_DATA2;

151 devselNX_n <= 0;

152 trdyNX_n <= 0;

153 end

154 TURN_AR:

155 if ( frame_i == 1 )

156 nxt_pci <= PCIIDLE;

157 else

158 nxt_pci <= TURN_AR;

159 endcase

160 end

161

162 // FSM control signals

163 assign adrpci = adrmem_i;

164

165 assign acking = (

166 ( wb_ack_i == 1 || wb_err_i == 1 ) ||

167 ( adrcfg_i == 1 && irdy_i == 0)

168 ) ? 1'b1 : 1'b0;

169

170 // FSM derived Control signals

171 assign idle = ( pst_pci <= PCIIDLE ) ? 1'b1 : 1'b0;

172 assign sdata1 = ( pst_pci <= S_DATA1 ) ? 1'b1 : 1'b0;

173 assign sdata2 = ( pst_pci <= S_DATA2 ) ? 1'b1 : 1'b0;

174 assign idleNX = ( nxt_pci <= PCIIDLE ) ? 1'b1 : 1'b0;

175 assign sdata1NX = ( nxt_pci <= S_DATA1 ) ? 1'b1 : 1'b0;

176 assign sdata2NX = ( nxt_pci <= S_DATA2 ) ? 1'b1 : 1'b0;

177 assign turnarNX = ( nxt_pci <= TURN_AR ) ? 1'b1 : 1'b0;

178

179 // PCI Data Output Enable

180 // always @( nrst_i or clk_i or cmd_i [0] or sdata1NX or turnarNX )

181 always @(negedge nrst_i or posedge clk_i)

182 begin

183 if ( nrst_i == 0 )

184 pcidOE <= 0;

185 else

186 if ( sdata1NX == 1 && cmd_i [0] == 0 )

187 pcidOE <= 1;

188 else

189 if ( turnarNX == 1 )

190 pcidOE <= 0;

191 end

192

193 assign pcidOE_o = pcidOE;

194

195 // PAR Output Enable

196 // PCI Read data phase

197 // PAR is valid 1 cicle after data is valid

198 // always @( nrst_i or clk_i or cmd_i [0] or sdata2NX or turnarNX )

199 always @(negedge nrst_i or posedge clk_i)

200 begin

201 if ( nrst_i == 0 )

202 parOE_o <= 0;

203 else

204 if ( ( sdata2NX == 1 || turnarNX == 1 ) && cmd_i [0] == 0 )

205 parOE_o <= 1;

206 else

207 parOE_o <= 0;

208 end

209

210 // Target s/t/s signals OE control

211 // targOE <= '1' when ( idle = '0' and adrpci = '1' ) else '0';

212 // always @( nrst_i or clk_i or sdata1NX or idleNX )

213 always @(negedge nrst_i or posedge clk_i)

214 begin

215 if ( nrst_i == 0 )

216 targOE <= 0;

217 else

218 if ( sdata1NX == 1 )

219 targOE <= 1;

220 else

221 if ( idleNX == 1 )

222 targOE <= 0;

223 end

224

225 // WHISBONE outs

226 assign wb_cyc_o = (adrmem_i == 1 && sdata1 == 1) ? 1'b1 : 1'b0;

227 assign wb_stb_o = (adrmem_i == 1 && sdata1 == 1 && irdy_i == 0 ) ? 1'b1 : 1'b0;

228

229 // PCI(Little endian) to WB(Big endian)

230 assign wb_sel_o [1] = (! cbe_i [0]) || (! cbe_i [2]);

231 assign wb_sel_o [0] = (! cbe_i [1]) || (! cbe_i [3]);

232

233 assign wb_we_o = cmd_i [0];

234

235 // Syncronized PCI outs

236 always @(negedge nrst_i or posedge clk_i)

237 begin

238 if( nrst_i == 0 )

239 begin

240 devsel <= 1;

241 trdy <= 1;

242 end

243 else

244 begin

245 devsel <= devselNX_n;

246 trdy <= trdyNX_n;

247 end

248 end

249

250 assign devsel_o = ( targOE == 1 ) ? devsel : 1'bZ;

251 assign trdy_o = ( targOE == 1 ) ? trdy : 1'bZ;

252

253 // rd/wr Configuration Space Registers

254 assign wrcfg_o = (

255 adrcfg_i == 1 &&

256 cmd_i [0] == 1 &&

257 sdata2 == 1

258 ) ? 1'b1 : 1'b0;

259

260 assign rdcfg = (

261 adrcfg_i == 1 &&

262 cmd_i [0] == 0 &&

263 (sdata1 == 1 || sdata2 == 1)

264 ) ? 1'b1 : 1'b0;

265

266 assign rdcfg_o = rdcfg;

267

268 // LoaD enable signals

269 assign pciadrLD_o = ! frame_i;

270 assign wbdatLD_o = wb_ack_i;

271

272 // Mux control signals

273 assign wbrgdMX_o = ! rdcfg;

274 assign wbd16MX_o = (cbe_i [3] == 0 || cbe_i [2] == 0) ? 1'b1 : 1'b0;

275

276 // debug outs

277 always @(negedge nrst_i or posedge clk_i)

278 begin

279 if ( nrst_i == 0 )

280 debug_init <= 0;

281 else

282 if (devsel == 0)

283 debug_init <= 1;

284 end

285

286 always @(negedge nrst_i or posedge clk_i)

287 begin

288 if ( nrst_i == 0 )

289 debug_access <= 0;

290 else

291 if (wb_stb_o == 1)

292 debug_access <= 1;

293 end

294

295 endmodule