1 //////////////////////////////////////////////////////////////////////
3 //// eth_rxcounters.v ////
5 //// This file is part of the Ethernet IP core project ////
6 //// http://www.opencores.org/projects/ethmac/ ////
9 //// - Igor Mohor (igorM@opencores.org) ////
10 //// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
11 //// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
13 //// All additional information is avaliable in the Readme.txt ////
16 //////////////////////////////////////////////////////////////////////
18 //// Copyright (C) 2001 Authors ////
20 //// This source file may be used and distributed without ////
21 //// restriction provided that this copyright statement is not ////
22 //// removed from the file and that any derivative work contains ////
23 //// the original copyright notice and the associated disclaimer. ////
25 //// This source file is free software; you can redistribute it ////
26 //// and/or modify it under the terms of the GNU Lesser General ////
27 //// Public License as published by the Free Software Foundation; ////
28 //// either version 2.1 of the License, or (at your option) any ////
29 //// later version. ////
31 //// This source is distributed in the hope that it will be ////
32 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
33 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
34 //// PURPOSE. See the GNU Lesser General Public License for more ////
37 //// You should have received a copy of the GNU Lesser General ////
38 //// Public License along with this source; if not, download it ////
39 //// from http://www.opencores.org/lgpl.shtml ////
41 //////////////////////////////////////////////////////////////////////
43 // CVS Revision History
45 // $Log: eth_rxcounters.v,v $
46 // Revision 1.1 2007-03-20 17:50:56 sithglan
49 // Revision 1.6 2005/02/21 11:00:57 igorm
52 // Revision 1.5 2002/02/15 11:13:29 mohor
53 // Format of the file changed a bit.
55 // Revision 1.4 2002/02/14 20:19:41 billditt
56 // Modified for Address Checking,
57 // addition of eth_addrcheck.v
59 // Revision 1.3 2002/01/23 10:28:16 mohor
60 // Link in the header changed.
62 // Revision 1.2 2001/10/19 08:43:51 mohor
63 // eth_timescale.v changed to timescale.v This is done because of the
64 // simulation of the few cores in a one joined project.
66 // Revision 1.1 2001/08/06 14:44:29 mohor
67 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
68 // Include files fixed to contain no path.
69 // File names and module names changed ta have a eth_ prologue in the name.
70 // File eth_timescale.v is used to define timescale
71 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
72 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
73 // and Mdo_OE. The bidirectional signal must be created on the top level. This
74 // is done due to the ASIC tools.
76 // Revision 1.1 2001/07/30 21:23:42 mohor
77 // Directory structure changed. Files checked and joind together.
79 // Revision 1.1 2001/06/27 21:26:19 mohor
80 // Initial release of the RxEthMAC module.
89 `include "timescale.v"
92 module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
93 MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
94 ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
95 ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
104 input [1:0] StateData;
115 output IFGCounterEq24; // IFG counter reaches 9600 ns (960 ns)
116 output [3:0] DlyCrcCnt; // Delayed CRC counter
117 output ByteCntEq0; // Byte counter = 0
118 output ByteCntEq1; // Byte counter = 1
119 output ByteCntEq2; // Byte counter = 2
120 output ByteCntEq3; // Byte counter = 3
121 output ByteCntEq4; // Byte counter = 4
122 output ByteCntEq5; // Byte counter = 5
123 output ByteCntEq6; // Byte counter = 6
124 output ByteCntEq7; // Byte counter = 7
125 output ByteCntGreat2; // Byte counter > 2
126 output ByteCntSmall7; // Byte counter < 7
127 output ByteCntMaxFrame; // Byte counter = MaxFL
128 output [15:0] ByteCntOut; // Byte counter
130 wire ResetByteCounter;
131 wire IncrementByteCounter;
132 wire ResetIFGCounter;
133 wire IncrementIFGCounter;
138 reg [4:0] IFGCounter;
140 wire [15:0] ByteCntDelayed;
144 assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
146 assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
147 (StatePreamble | StateSFD | StateIdle & ~Transmitting |
148 StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
152 always @ (posedge MRxClk or posedge Reset)
155 ByteCnt[15:0] <= #Tp 16'h0;
159 ByteCnt[15:0] <= #Tp 16'h0;
161 if(IncrementByteCounter)
162 ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
166 assign ByteCntDelayed = ByteCnt + 3'h4;
167 assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
169 assign ByteCntEq0 = ByteCnt == 16'h0;
170 assign ByteCntEq1 = ByteCnt == 16'h1;
171 assign ByteCntEq2 = ByteCnt == 16'h2;
172 assign ByteCntEq3 = ByteCnt == 16'h3;
173 assign ByteCntEq4 = ByteCnt == 16'h4;
174 assign ByteCntEq5 = ByteCnt == 16'h5;
175 assign ByteCntEq6 = ByteCnt == 16'h6;
176 assign ByteCntEq7 = ByteCnt == 16'h7;
177 assign ByteCntGreat2 = ByteCnt > 16'h2;
178 assign ByteCntSmall7 = ByteCnt < 16'h7;
179 assign ByteCntMax = ByteCnt == 16'hffff;
180 assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
183 assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop;
185 assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
187 always @ (posedge MRxClk or posedge Reset)
190 IFGCounter[4:0] <= #Tp 5'h0;
194 IFGCounter[4:0] <= #Tp 5'h0;
196 if(IncrementIFGCounter)
197 IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1;
203 assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
206 always @ (posedge MRxClk or posedge Reset)
209 DlyCrcCnt[3:0] <= #Tp 4'h0;
212 if(DlyCrcCnt[3:0] == 4'h9)
213 DlyCrcCnt[3:0] <= #Tp 4'h0;
215 if(DlyCrcEn & StateSFD)
216 DlyCrcCnt[3:0] <= #Tp 4'h1;
218 if(DlyCrcEn & (|DlyCrcCnt[3:0]))
219 DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1;