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1 //////////////////////////////////////////////////////////////////////
2 //// ////
3 //// File name: pci_rst_int.v ////
4 //// ////
5 //// This file is part of the "PCI bridge" project ////
6 //// http://www.opencores.org/cores/pci/ ////
7 //// ////
8 //// Author(s): ////
9 //// - Tadej Markovic, tadej@opencores.org ////
10 //// ////
11 //// All additional information is avaliable in the README.txt ////
12 //// file. ////
13 //// ////
14 //// ////
15 //////////////////////////////////////////////////////////////////////
16 //// ////
17 //// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
18 //// ////
19 //// This source file may be used and distributed without ////
20 //// restriction provided that this copyright statement is not ////
21 //// removed from the file and that any derivative work contains ////
22 //// the original copyright notice and the associated disclaimer. ////
23 //// ////
24 //// This source file is free software; you can redistribute it ////
25 //// and/or modify it under the terms of the GNU Lesser General ////
26 //// Public License as published by the Free Software Foundation; ////
27 //// either version 2.1 of the License, or (at your option) any ////
28 //// later version. ////
29 //// ////
30 //// This source is distributed in the hope that it will be ////
31 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
33 //// PURPOSE. See the GNU Lesser General Public License for more ////
34 //// details. ////
35 //// ////
36 //// You should have received a copy of the GNU Lesser General ////
37 //// Public License along with this source; if not, download it ////
38 //// from http://www.opencores.org/lgpl.shtml ////
39 //// ////
40 //////////////////////////////////////////////////////////////////////
41 //
42 // CVS Revision History
43 //
44 // $Log: pci_rst_int.v,v $
45 // Revision 1.1 2007-03-20 17:50:56 sithglan
46 // add shit
47 //
48 // Revision 1.3 2003/12/19 11:11:30 mihad
49 // Compact PCI Hot Swap support added.
50 // New testcases added.
51 // Specification updated.
52 // Test application changed to support WB B3 cycles.
53 //
54 // Revision 1.2 2003/01/27 16:49:31 mihad
55 // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
56 //
57 // Revision 1.1 2002/02/01 14:43:31 mihad
58 // *** empty log message ***
59 //
60 //
61 //
62
63 `include "pci_constants.v"
64
65 // synopsys translate_off
66 `include "timescale.v"
67 // synopsys translate_on
68
69 // Module is used to switch appropriate reset and interrupt signals with few logic
70 module pci_rst_int
71 (
72 clk_in,
73 // reset signals
74 rst_i,
75 pci_rstn_in,
76 conf_soft_res_in,
77 reset,
78 pci_rstn_out,
79 pci_rstn_en_out,
80 rst_o,
81 // interrupt signals
82 pci_intan_in,
83 conf_int_in,
84 int_i,
85 pci_intan_out,
86 pci_intan_en_out,
87 int_o,
88 conf_isr_int_prop_out,
89 init_complete_in
90 );
91
92 input clk_in;
93 // RESET inputs and outputs
94 input rst_i;
95 input pci_rstn_in;
96 input conf_soft_res_in;
97 output reset;
98 output pci_rstn_out;
99 output pci_rstn_en_out;
100 output rst_o;
101
102 // INTERRUPT inputs and outputs
103 input pci_intan_in;
104 input conf_int_in;
105 input int_i;
106 output pci_intan_out;
107 output pci_intan_en_out;
108 output int_o;
109 output conf_isr_int_prop_out;
110
111 input init_complete_in ;
112
113 /*--------------------------------------------------------------------------------------------------------
114 RESET logic
115 --------------------------------------------------------------------------------------------------------*/
116 assign pci_rstn_out = 1'b0 ;
117 // host implementation of the bridge gets its reset from WISHBONE bus - RST_I and propagates it to PCI bus
118 `ifdef HOST
119 assign reset = rst_i ;
120 `ifdef ACTIVE_LOW_OE
121 assign pci_rstn_en_out = ~(rst_i || conf_soft_res_in) ;
122 `else
123 assign pci_rstn_en_out = rst_i || conf_soft_res_in ;
124 `endif
125 assign rst_o = 1'b0 ;
126 `else
127 // guest implementation of the bridge gets its reset from PCI bus - RST# and propagates it to WISHBONE bus
128 `ifdef GUEST
129 assign reset = ~pci_rstn_in ;
130 assign rst_o = (~pci_rstn_in) || conf_soft_res_in ;
131 `ifdef ACTIVE_LOW_OE
132 assign pci_rstn_en_out = 1'b1 ; // disabled
133 `else
134 assign pci_rstn_en_out = 1'b0 ; // disabled
135 `endif
136 `endif
137 `endif
138
139 /*--------------------------------------------------------------------------------------------------------
140 INTERRUPT logic
141 --------------------------------------------------------------------------------------------------------*/
142 assign pci_intan_out = 1'b0 ;
143 // host implementation of the bridge gets its interrupt from PCI bus - INTA# and propagates it to WISHBONE bus
144 `ifdef HOST
145 assign conf_isr_int_prop_out = ~pci_intan_in ;
146 assign int_o = conf_int_in ;
147 `ifdef ACTIVE_LOW_OE
148 assign pci_intan_en_out = 1'b1 ; // disabled
149 `else
150 assign pci_intan_en_out = 1'b0 ; // disabled
151 `endif
152 `else
153 // guest implementation of the bridge gets its interrupt from WISHBONE bus - INT_I and propagates it to PCI bus
154 `ifdef GUEST
155 wire interrupt_a_en;
156 pci_out_reg inta
157 (
158 .reset_in ( reset ),
159 .clk_in ( clk_in) ,
160 .dat_en_in ( 1'b1 ),
161 .en_en_in ( init_complete_in ),
162 .dat_in ( 1'b0 ) , // active low
163 .en_in ( conf_int_in ) ,
164 .en_out ( interrupt_a_en ),
165 .dat_out ( )
166 );
167 assign conf_isr_int_prop_out = int_i ;
168 assign int_o = 1'b0 ;
169 assign pci_intan_en_out = interrupt_a_en ;
170 `endif
171 `endif
172
173
174 endmodule
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