[raggedstone] / ethernet / source / pci / pci_serr_crit.v

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  File name "serr_crit.v"                                     ////
////                                                              ////
////  This file is part of the "PCI bridge" project               ////
////  http://www.opencores.org/cores/pci/                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Miha Dolenc (mihad@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the README       ////
////  file.                                                       ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
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//// This source file may be used and distributed without         ////
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//// the original copyright notice and the associated disclaimer. ////
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//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
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//// You should have received a copy of the GNU Lesser General    ////
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//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: pci_serr_crit.v,v $
// Revision 1.1  2007-03-20 17:50:56  sithglan
// add shit
//
// Revision 1.2  2003/02/13 18:26:33  mihad
// Cleaned up the code. No functional changes.
//
// Revision 1.1  2003/01/27 16:49:31  mihad
// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
//
// Revision 1.3  2002/02/01 15:25:13  mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.2  2001/10/05 08:14:30  mihad
// Updated all files with inclusion of timescale file for simulation purposes.
//
// Revision 1.1.1.1  2001/10/02 15:33:47  mihad
// New project directory structure
//
//

// module is used to separate logic which uses criticaly constrained inputs from slower logic.
// It is used to synthesize critical timing logic separately with faster cells or without optimization

// This one is used in parity generator/checker for system error (SERR#) output

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on

module pci_serr_crit
(
    serr_out,
    non_critical_par_in,
    pci_par_in,
    serr_check_in
);

output  serr_out ;

input   non_critical_par_in,
        pci_par_in,
        serr_check_in ;

assign serr_out = ~(serr_check_in && ( non_critical_par_in ^ pci_par_in )) ;

endmodule