-- J.STELZNER -- INFORMATIK-3 LABOR -- 23.08.2006 -- File: DATA_MUX.VHD library ieee ; use ieee.std_logic_1164.all ; entity DATA_MUX is port ( READ_SEL :in std_logic_vector( 1 downto 0); ADDR_REG :in std_logic_vector(31 downto 0); CBE_REGn :in std_logic_vector( 3 downto 0); MUX_IN_XX0 :in std_logic_vector( 7 downto 0); MUX_IN_XX1 :in std_logic_vector( 7 downto 0); MUX_IN_XX2 :in std_logic_vector( 7 downto 0); MUX_IN_XX3 :in std_logic_vector( 7 downto 0); MUX_IN_XX4 :in std_logic_vector( 7 downto 0); MUX_IN_XX5 :in std_logic_vector( 7 downto 0); MUX_IN_XX6 :in std_logic_vector( 7 downto 0); MUX_IN_XX7 :in std_logic_vector( 7 downto 0); MUX_OUT :out std_logic_vector(31 downto 0); READ_XX1_0 :out std_logic; READ_XX3_2 :out std_logic; READ_XX5_4 :out std_logic; READ_XX7_6 :out std_logic --READ_FIFO :out std_logic ); end entity DATA_MUX ; architecture DATA_MUX_DESIGN of DATA_MUX is signal MUX :std_logic_vector(31 downto 0); signal SEL :std_logic_vector( 7 downto 0); signal SIG_READ_XX1_0 :std_logic; signal SIG_READ_XX3_2 :std_logic; signal SIG_READ_XX5_4 :std_logic; signal SIG_READ_XX7_6 :std_logic; begin SEL <= ADDR_REG(3 downto 2) & CBE_REGn & READ_SEL ; SIG_READ_XX1_0 <= '1' when SEL = "00110011" else '0'; SIG_READ_XX3_2 <= '1' when SEL = "00001111" else '0'; SIG_READ_XX5_4 <= '1' when SEL = "01110011" else '0'; SIG_READ_XX7_6 <= '1' when SEL = "01001111" else '0'; MUX <= (X"00" & X"00" & MUX_IN_XX1 & MUX_IN_XX0) when SIG_READ_XX1_0 = '1' else (MUX_IN_XX3 & MUX_IN_XX2 & X"00" & X"00" ) when SIG_READ_XX3_2 = '1' else (X"00" & X"00" & MUX_IN_XX5 & MUX_IN_XX4) when SIG_READ_XX5_4 = '1' else (MUX_IN_XX7 & MUX_IN_XX6 & X"00" & X"00" ) when SIG_READ_XX7_6 = '1' else (others => '0'); -- MUX <= (X"01" & X"23" & MUX_IN_XX1 & MUX_IN_XX0) when SIG_READ_XX1_0 = '1' else -- (MUX_IN_XX3 & MUX_IN_XX2 & X"45" & X"67" ) when SIG_READ_XX3_2 = '1' else -- (X"89" & X"AB" & MUX_IN_XX5 & MUX_IN_XX4) when SIG_READ_XX5_4 = '1' else -- (MUX_IN_XX7 & MUX_IN_XX6 & X"CD" & X"EF" ) when SIG_READ_XX7_6 = '1' else -- (others => '0'); MUX_OUT <= MUX ; READ_XX1_0 <= SIG_READ_XX1_0; READ_XX3_2 <= SIG_READ_XX3_2; READ_XX5_4 <= SIG_READ_XX5_4; READ_XX7_6 <= SIG_READ_XX7_6; --READ_FIFO <= SIG_READ_XX3_2 or SIG_READ_XX5_4;--SIG_READ_XX5_4 nur fuer test end architecture DATA_MUX_DESIGN ;