-- J.STELZNER -- INFORMATIK-3 LABOR -- 23.08.2006 -- File: CONT_FSM.VHD library ieee; use ieee.std_logic_1164.all; entity CONT_FSM is port ( PCI_CLOCK :in std_logic; PCI_RSTn :in std_logic; IO_READ :in std_logic; IO_WRITE :in std_logic; CONF_READ :in std_logic; CONF_WRITE :in std_logic; FIFO_READ :in std_logic; READ :out std_logic;--> MUX_SEL(1) , OE_PCI_AD PERR_CHECK :out std_logic; DEVSELn :out std_logic; OE_PCI_PAR :out std_logic; OE_PCI_PERR :out std_logic; TRDYn :out std_logic; PCI_TRDYn :out std_logic; -- s/t/s PCI_STOPn :out std_logic; -- s/t/s PCI_DEVSELn :out std_logic; -- s/t/s FIFO_RDn :out std_logic ); end entity CONT_FSM; architecture CONT_FSM_DESIGN of CONT_FSM is --********************************************************** --*** CONTROL FSM CODIERUNG *** --********************************************************** -- -- -- -- |----------- HELP -- ||---------- FIFO_READn -- |||--------- OE_PCI_PERR -- ||||-------- PERR_CHECK -- |||||------- TRDYn -- ||||||------ STOPn -- |||||||----- DEVSELn -- ||||||||---- OE_PCI_PAR -- |||||||||--- OE_CONTROL -- ||||||||||-- READ / MUX_SEL(1) / OE_PCI_AD -- |||||||||| constant ST_IDLE :std_logic_vector (9 downto 0) := "0100111000";-- 138 constant ST_READ_1 :std_logic_vector (9 downto 0) := "0100110011";-- 133 constant ST_READ_2 :std_logic_vector (9 downto 0) := "0100000111";-- 107 constant ST_READ_3 :std_logic_vector (9 downto 0) := "0100111111";-- 13F constant ST_RD_FIFO_1 :std_logic_vector (9 downto 0) := "0000110011";-- 033 constant ST_RD_FIFO_2 :std_logic_vector (9 downto 0) := "1100110011";-- 233 constant ST_WRITE_1 :std_logic_vector (9 downto 0) := "0111110010";-- 1F2 constant ST_WRITE_2 :std_logic_vector (9 downto 0) := "0110000010";-- 182 constant ST_WRITE_3 :std_logic_vector (9 downto 0) := "0110111010";-- 1BA signal CONTROL_STATE :std_logic_vector (9 downto 0); --signal DEVSELn :std_logic; signal STOPn :std_logic; --signal TRDYn :std_logic; --************************************************************ --*** FSM SPEICHER-AUTOMAT *** --************************************************************ attribute syn_state_machine : boolean; attribute syn_state_machine of CONTROL_STATE : signal is false; begin --********************************************************** --*** CONTROL FSM *** --********************************************************** process (PCI_CLOCK, PCI_RSTn) begin if PCI_RSTn = '0' then CONTROL_STATE <= ST_IDLE; elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then case CONTROL_STATE is when ST_IDLE => if IO_READ = '1' then CONTROL_STATE <= ST_READ_1; elsif CONF_READ = '1' then CONTROL_STATE <= ST_READ_1; elsif IO_WRITE = '1' then CONTROL_STATE <= ST_WRITE_1; elsif CONF_WRITE = '1' then CONTROL_STATE <= ST_WRITE_1; else CONTROL_STATE <= ST_IDLE; end if; -- when ST_READ_1 => -- CONTROL_STATE <= ST_READ_2; when ST_READ_1 => if FIFO_READ = '1' then CONTROL_STATE <= ST_RD_FIFO_1; else CONTROL_STATE <= ST_READ_2; end if; when ST_READ_2 => CONTROL_STATE <= ST_READ_3; when ST_READ_3 => CONTROL_STATE <= ST_IDLE; when ST_RD_FIFO_1=> CONTROL_STATE <= ST_RD_FIFO_2; when ST_RD_FIFO_2=> CONTROL_STATE <= ST_READ_2; when ST_WRITE_1 => CONTROL_STATE <= ST_WRITE_2; when ST_WRITE_2 => CONTROL_STATE <= ST_WRITE_3; when ST_WRITE_3 => CONTROL_STATE <= ST_IDLE; when others => CONTROL_STATE <= ST_IDLE; end case; -- COMM_STATE end if; -- CLOCK end process; -- PROCESS READ <= CONTROL_STATE(0); --OE_CONTROL <= CONTROL_STATE(1); OE_PCI_PAR <= CONTROL_STATE(2); DEVSELn <= CONTROL_STATE(3); STOPn <= CONTROL_STATE(4); TRDYn <= CONTROL_STATE(5); PERR_CHECK <= CONTROL_STATE(6); OE_PCI_PERR <= CONTROL_STATE(7); FIFO_RDn <= CONTROL_STATE(8); PCI_DEVSELn <= CONTROL_STATE(3) when CONTROL_STATE(1) = '1' else 'Z'; PCI_STOPn <= STOPn when CONTROL_STATE(1) = '1' else 'Z'; PCI_TRDYn <= CONTROL_STATE(5) when CONTROL_STATE(1) = '1' else 'Z'; end architecture CONT_FSM_DESIGN;