library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity heartbeat is
generic (
	divider : integer := 33000000
);

port (
	clk_i : in std_logic;
	nrst_i : in std_logic;
	led_o : out std_logic
);   

end heartbeat;

architecture rtl of heartbeat is
begin

process(clk_i, nrst_i)
variable counter : std_logic_vector(31 downto 0);
variable state : std_logic := '0';
begin

if (clk_i'event AND clk_i = '1') then
	if nrst_i = '0' then
		counter := (others => '0');
        else
		led_o <= state;
		counter := counter + 1;
		if counter = divider then
			state := not state;
	        end if;
	end if;
end if;
end process;
end architecture;