-- J.STELZNER -- INFORMATIK-3 LABOR -- 23.08.2006 -- File: FLAG_BUS.VHD library IEEE; use IEEE.std_logic_1164.all; entity FLAG_BUS is port ( PCI_CLOCK :in std_logic; KONS_1 :in std_logic; FLAG_IN_0 :in std_logic; R_EFn :in std_logic; R_HFn :in std_logic; R_FFn :in std_logic; FLAG_IN_4 :in std_logic; S_EFn :in std_logic; S_HFn :in std_logic; S_FFn :in std_logic; HOLD :in std_logic; SYNC_FLAG :out std_logic_vector (7 downto 0) ); end entity FLAG_BUS; architecture FLAG_BUS_DESIGN of FLAG_BUS is signal FF1_S_EFn :std_logic; signal FF1_S_HFn :std_logic; signal FF1_S_FFn :std_logic; signal FF1_R_EFn :std_logic; signal FF1_R_HFn :std_logic; signal FF1_R_FFn :std_logic; signal FF2_S_EFn :std_logic; signal FF2_S_HFn :std_logic; signal FF2_S_FFn :std_logic; signal FF2_R_EFn :std_logic; signal FF2_R_HFn :std_logic; signal FF2_R_FFn :std_logic; begin process (PCI_CLOCK) begin if (PCI_CLOCK'event and PCI_CLOCK = '1') then FF1_S_EFn <= not S_EFn; FF1_S_HFn <= not S_HFn; FF1_S_FFn <= not S_FFn; FF1_R_EFn <= not R_EFn; FF1_R_HFn <= not R_HFn; FF1_R_FFn <= not R_FFn; end if; end process; process (PCI_CLOCK) begin if (PCI_CLOCK'event and PCI_CLOCK = '1') then if HOLD = '0' then FF2_S_EFn <= FF1_S_EFn; FF2_S_HFn <= FF1_S_HFn; FF2_S_FFn <= FF1_S_FFn; FF2_R_EFn <= FF1_R_EFn; FF2_R_HFn <= FF1_R_HFn; FF2_R_FFn <= FF1_R_FFn; elsif HOLD = '1' then FF2_S_EFn <= FF2_S_EFn; FF2_S_HFn <= FF2_S_HFn; FF2_S_FFn <= FF2_S_FFn; FF2_R_EFn <= FF2_R_EFn; FF2_R_HFn <= FF2_R_HFn; FF2_R_FFn <= FF2_R_FFn; end if; end if; end process; SYNC_FLAG(0) <= FLAG_IN_0; SYNC_FLAG(1) <= FF2_R_EFn; SYNC_FLAG(2) <= FF2_R_HFn; SYNC_FLAG(3) <= FF2_R_FFn; SYNC_FLAG(4) <= FLAG_IN_4; SYNC_FLAG(5) <= FF2_S_EFn; SYNC_FLAG(6) <= FF2_S_HFn; SYNC_FLAG(7) <= FF2_S_FFn; end architecture FLAG_BUS_DESIGN;