# BEGIN Project Options SET addpads = False SET asysymbol = False SET busformat = BusFormatAngleBracketNotRipped SET createndf = False SET designentry = VHDL SET device = xc3s1500 SET devicefamily = spartan3 SET flowvendor = Other SET formalverification = False SET foundationsym = False SET implementationfiletype = Ngc SET package = fg456 SET removerpms = False SET simulationfiles = Structural SET speedgrade = -4 SET verilogsim = False SET vhdlsim = True # END Project Options # BEGIN Select SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.02.a # END Select # BEGIN Parameters CSET asynchronous_input_port_width=4 CSET asynchronous_output_port_width=8 CSET component_name=vio CSET enable_asynchronous_input_port=true CSET enable_asynchronous_output_port=false CSET enable_synchronous_input_port=false CSET enable_synchronous_output_port=true CSET invert_clock_input=false CSET synchronous_input_port_width=8 CSET synchronous_output_port_width=1 # END Parameters GENERATE