library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity dhwk is
port (

    -- General 
    PCI_CLK     : in std_logic;
    PCI_nRES    : in std_logic;
    
    -- PCI target 32bits
    PCI_AD      : inout std_logic_vector(31 downto 0);
    PCI_CBE     : in std_logic_vector(3 downto 0);
    PCI_PAR     : out std_logic;  
    PCI_nFRAME  : in std_logic;
    PCI_nIRDY   : in std_logic;
    PCI_nTRDY   : out std_logic;
    PCI_nDEVSEL : out std_logic;
    PCI_nSTOP   : out std_logic;
    PCI_IDSEL   : in std_logic;
    PCI_nPERR   : out std_logic;
    PCI_nSERR   : out std_logic;
    PCI_nINT    : out std_logic;
 
	-- debug signals
	LED3	: out std_logic;
	LED2	: out std_logic;
	LED4		: out std_logic;
	LED5		: out std_logic

);
end dhwk;


architecture dhwk_arch of dhwk is


component pci32tlite
port (

    -- General 
    clk33       : in std_logic;
    nrst	    : in std_logic;
    
    -- PCI target 32bits
    ad          : inout std_logic_vector(31 downto 0);
    cbe         : in std_logic_vector(3 downto 0);
    par         : out std_logic;  
    frame       : in std_logic;
    irdy        : in std_logic;
    trdy        : out std_logic;
    devsel      : out std_logic;
    stop        : out std_logic;
    idsel       : in std_logic;
    perr        : out std_logic;
    serr        : out std_logic;
    intb        : out std_logic;
      
	-- Master whisbone
    wb_adr_o     : out std_logic_vector(24 downto 1);     
	wb_dat_i     : in std_logic_vector(15 downto 0);
    wb_dat_o     : out std_logic_vector(15 downto 0);
	wb_sel_o     : out std_logic_vector(1 downto 0);
    wb_we_o      : out std_logic;
	wb_stb_o     : out std_logic;
	wb_cyc_o     : out std_logic;
	wb_ack_i     : in std_logic;
	wb_err_i     : in std_logic;
	wb_int_i     : in std_logic;

	-- debug signals
	debug_init	 : out std_logic;
	debug_access : out std_logic 

	);
end component;

component heartbeat
port (
	clk_i : in std_logic;
	nrst_i : in std_logic;
	led2_o : out std_logic;
	led3_o : out std_logic;
	led4_o : out std_logic;
	led5_o : out std_logic
);
end component;

component generic_fifo_sc_a
port (
	clk		: in std_logic;
	rst		: in std_logic;
	clr		: in std_logic;
	din		: in std_logic_vector(7 downto 0);
	we		: in std_logic;
	dout		: out std_logic_vector(7 downto 0);
	re		: in std_logic;
	full		: out std_logic;
	full_r		: out std_logic;
	empty		: out std_logic;
	empty_r		: out std_logic;
	full_n		: out std_logic;
	full_n_r	: out std_logic;
	empty_n		: out std_logic;
	empty_n_r	: out std_logic;
	level		: out std_logic_vector(1 downto 0)
);
end component;

component wb_fifo
port (
	clk_i		: in std_logic;
	nrst_i		: in std_logic;
	
	wb_adr_i	: in std_logic_vector(24 downto 1);
	wb_dat_o	: out std_logic_vector(15 downto 0);
	wb_dat_i	: in std_logic_vector(15 downto 0);
	wb_sel_i	: in std_logic_vector(1 downto 0);
	wb_we_i		: in std_logic;
	wb_stb_i	: in std_logic;
	wb_cyc_i	: in std_logic;
	wb_ack_o	: out std_logic;
	wb_err_o	: out std_logic;
	wb_int_o	: out std_logic;
	
	fifo_data_i	: in std_logic_vector(7 downto 0);
	fifo_data_o     : out std_logic_vector(7 downto 0);

	fifo_we_o	: out std_logic;
	fifo_re_o	: out std_logic
);
end component;

signal 	wb_adr :		std_logic_vector(24 downto 1);   
signal	wb_dat_out :	std_logic_vector(15 downto 0);
signal 	wb_dat_in :		std_logic_vector(15 downto 0);
signal	wb_sel :		std_logic_vector(1 downto 0);
signal  wb_we :			std_logic;
signal	wb_stb :		std_logic;
signal	wb_cyc :		std_logic;
signal	wb_ack :		std_logic;
signal	wb_err :		std_logic;
signal	wb_int :		std_logic;

signal fifo_din		: std_logic_vector(7 downto 0);
signal fifo_dout	: std_logic_vector(7 downto 0);
signal fifo_we		: std_logic;
signal fifo_re		: std_logic;



begin

u_pci: component pci32tlite
port map(
    	clk33 =>		PCI_CLK,
    	nrst =>			PCI_nRES,
    	ad =>			PCI_AD,
    	cbe =>			PCI_CBE,
    	par =>			PCI_PAR,
    	frame =>		PCI_nFRAME,
    	irdy =>     	PCI_nIRDY,
    	trdy =>     	PCI_nTRDY,
    	devsel =>   	PCI_nDEVSEL,
    	stop =>     	PCI_nSTOP,
    	idsel =>    	PCI_IDSEL,
    	perr =>     	PCI_nPERR,
    	serr =>     	PCI_nSERR,
    	intb =>     	PCI_nINT,
    	wb_adr_o =>		wb_adr,	   
		wb_dat_i =>		wb_dat_out,
    	wb_dat_o =>  	wb_dat_in,
		wb_sel_o =>		wb_sel,		
    	wb_we_o =>		wb_we,
		wb_stb_o =>		wb_stb,	
		wb_cyc_o =>		wb_cyc,
		wb_ack_i =>		wb_ack,
		wb_err_i =>		wb_err,
		wb_int_i =>		wb_int
--		debug_init =>	LED3,
--		debug_access =>	LED2
);

my_generic_fifo: component generic_fifo_sc_a
port map(
	clk		=> PCI_CLK,
	rst		=> PCI_nRES,
	clr		=> '0',
	din		=> fifo_din,
	we		=> fifo_we,
	dout		=> fifo_dout,
	re		=> fifo_re
--	full		=> ,
--	full_r		=> ,
--	empty		=> ,
--	empty_r		=> ,
--	full_n		=> ,
--	full_n_r	=> ,
--	empty_n		=> ,
--	empty_n_r	=> ,
--	level		=> ,
);

my_fifo: component wb_fifo
port map(
	clk_i		 => PCI_CLK,
	nrst_i		 => PCI_nRES,

	wb_adr_i	 => wb_adr,
	wb_dat_o	 => wb_dat_out,
	wb_dat_i	 => wb_dat_in,
	wb_sel_i	 => wb_sel,
	wb_we_i		 => wb_we,
	wb_stb_i	 => wb_stb,
	wb_cyc_i	 => wb_cyc,
	wb_ack_o	 => wb_ack,
	wb_err_o	 => wb_err,
	wb_int_o	 => wb_int,

	fifo_data_i	 => fifo_dout,
	fifo_data_o      => fifo_din,

	fifo_we_o	 => fifo_we,
	fifo_re_o	 => fifo_re
);

my_heartbeat: component heartbeat
port map( 
	clk_i => PCI_CLK,
	nrst_i => PCI_nRES,
	led2_o => LED2,
	led3_o => LED3,
	led4_o => LED4,
	led5_o => LED5
);

end dhwk_arch;