-- J.STELZNER -- INFORMATIK-3 LABOR -- 23.08.2006 -- File: COMM_DEC.VHD library ieee; use ieee.std_logic_1164.all ; entity COMM_DEC is port ( PCI_CLOCK :in std_logic; PCI_RSTn :in std_logic; MY_ADDR :in std_logic; IDSEL_REG :in std_logic; FRAME_REGn :in std_logic; IO_SPACE :in std_logic; AD_REG :in std_logic_vector(31 downto 0); CBE_REGn :in std_logic_vector( 3 downto 0); LAR :out std_logic; --LOAD_ADDR_REG IO_READ :out std_logic; IO_WRITE :out std_logic; CONF_READ :out std_logic; CONF_WRITE :out std_logic; SERR_CHECK :out std_logic ); end entity COMM_DEC ; architecture COMM_DEC_DESIGN of COMM_DEC is --PCI Bus Commands --C/BE[3..0] Command Type -------------------------------------- -- 0000 Interrupt Acknowledge -- 0001 Special Cycle -- 0010 I/O Read -- 0011 I/O Write -- 0100 Reserved -- 0101 Reserved -- 0110 Memory Read -- 0111 Memory Write -- -- 1000 Reserved -- 1001 Reserved -- 1010 Configuration Read -- 1011 Configuration Write -- 1100 Memory Read Multiple -- 1101 Dual Address Cycle -- 1110 Memory Read Line -- 1111 Memory Write and Invalidate --PCI Byte Enable --C/BE[3..0] gueltige Datenbits ------------------------------- -- 0000 AD 31..0 -- 1000 AD 23..0 -- 1100 AD 15..0 -- 1110 AD 7..0 constant cmd_int_ack :std_logic_vector(3 downto 0) := "0000"; constant cmd_sp_cyc :std_logic_vector(3 downto 0) := "0001"; constant cmd_io_read :std_logic_vector(3 downto 0) := "0010"; constant cmd_io_write :std_logic_vector(3 downto 0) := "0011"; constant cmd_res_4 :std_logic_vector(3 downto 0) := "0100"; constant cmd_res_5 :std_logic_vector(3 downto 0) := "0101"; constant cmd_mem_read :std_logic_vector(3 downto 0) := "0110"; constant cmd_mem_write :std_logic_vector(3 downto 0) := "0111"; constant cmd_res_8 :std_logic_vector(3 downto 0) := "1000"; constant cmd_res_9 :std_logic_vector(3 downto 0) := "1001"; constant cmd_conf_read :std_logic_vector(3 downto 0) := "1010"; constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011"; constant cmd_mem_read_m :std_logic_vector(3 downto 0) := "1100"; constant cmd_du_adr_cyc :std_logic_vector(3 downto 0) := "1101"; constant cmd_mem_read_l :std_logic_vector(3 downto 0) := "1110"; constant cmd_mem_write_i :std_logic_vector(3 downto 0) := "1111"; signal START :std_logic; signal FRAME_REG_REGn :std_logic; signal SIG_IO_READ :std_logic; signal SIG_IO_WRITE :std_logic; signal SIG_CONF_READ :std_logic; signal SIG_CONF_WRITE :std_logic; begin process (PCI_CLOCK, PCI_RSTn) begin if PCI_RSTn = '0' then FRAME_REG_REGn <= '1'; elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then FRAME_REG_REGn <= FRAME_REGn; end if; end process; START <= (not FRAME_REGn) and FRAME_REG_REGn; SIG_IO_READ <= '1' when START = '1' and IO_SPACE = '1' and CBE_REGn = cmd_io_read and MY_ADDR = '1' else '0'; SIG_IO_WRITE <= '1' when START = '1' and IO_SPACE = '1' and CBE_REGn = cmd_io_write and MY_ADDR = '1' else '0'; SIG_CONF_READ <= '1' when START = '1' and AD_REG(1 downto 0) = "00" and CBE_REGn = cmd_conf_read and IDSEL_REG = '1' else '0'; SIG_CONF_WRITE <= '1' when START = '1' and AD_REG(1 downto 0) = "00" and CBE_REGn = cmd_conf_write and IDSEL_REG = '1' else '0'; LAR <= START; SERR_CHECK <= SIG_IO_READ or SIG_IO_WRITE or SIG_CONF_READ or SIG_CONF_WRITE; IO_READ <= SIG_IO_READ; IO_WRITE <= SIG_IO_WRITE; CONF_READ <= SIG_CONF_READ; CONF_WRITE <= SIG_CONF_WRITE; end architecture COMM_DEC_DESIGN;