////////////////////////////////////////////////////////////////////// //// //// //// File name "delayed_write_reg.v" //// //// //// //// This file is part of the "PCI bridge" project //// //// http://www.opencores.org/cores/pci/ //// //// //// //// Author(s): //// //// - Miha Dolenc (mihad@opencores.org) //// //// //// //// All additional information is avaliable in the README //// //// file. //// //// //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: pci_delayed_write_reg.v,v $ // Revision 1.1 2007-03-20 17:50:56 sithglan // add shit // // Revision 1.1 2003/01/27 16:49:31 mihad // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. // // Revision 1.3 2002/02/01 15:25:12 mihad // Repaired a few bugs, updated specification, added test bench files and design document // // Revision 1.2 2001/10/05 08:14:28 mihad // Updated all files with inclusion of timescale file for simulation purposes. // // Revision 1.1.1.1 2001/10/02 15:33:46 mihad // New project directory structure // // `include "pci_constants.v" // synopsys translate_off `include "timescale.v" // synopsys translate_on module pci_delayed_write_reg ( reset_in, req_clk_in, comp_wdata_out, req_we_in, req_wdata_in ); // system inputs input reset_in, req_clk_in ; // request clock input output [31:0] comp_wdata_out ; // data output input req_we_in ; // write enable input input [31:0] req_wdata_in ; // data input - latched with posedge of req_clk_in when req_we_in is high reg [31:0] comp_wdata_out ; // write request operation always@(posedge req_clk_in or posedge reset_in) begin if (reset_in) comp_wdata_out <= #`FF_DELAY 32'h0000_0000 ; else if (req_we_in) comp_wdata_out <= #`FF_DELAY req_wdata_in ; end endmodule // DELAYED_WRITE_REG