LIBRARY ieee; USE ieee.std_logic_1164.ALL; Library UNISIM; use UNISIM.vcomponents.all; entity ethernet is PORT( PCI_AD : INOUT std_logic_vector(31 downto 0); PCI_CLOCK : IN std_logic; PCI_IDSEL : IN std_logic; PCI_CBEn : INOUT std_logic_vector (3 downto 0); PCI_FRAMEn : INOUT std_logic; PCI_IRDYn : INOUT std_logic; PCI_RSTn : INOUT std_logic; PCI_DEVSELn : INOUT std_logic; PCI_INTAn : INOUT std_logic; PCI_PERRn : INOUT std_logic; PCI_SERRn : INOUT std_logic; PCI_STOPn : INOUT std_logic; PCI_TRDYn : INOUT std_logic; PCI_PAR : INOUT std_logic; PCI_REQn : OUT std_logic; PCI_GNTn : IN std_logic; MTX_CLK_PAD_I : IN std_logic; MTXD_PAD_O : OUT std_logic_vector (3 downto 0); MTXEN_PAD_O : OUT std_logic; MRX_CLK_PAD_I : IN std_logic; MRXD_PAD_I : IN std_logic_vector (3 downto 0); MRXDV_PAD_I : IN std_logic; MRXERR_PAD_I : IN std_logic; MCOLL_PAD_I : IN std_logic; MCRS_PAD_I : IN std_logic; MD_PAD_IO : INOUT std_logic; MDC_PAD_O : OUT std_logic; PHY_CLOCK : OUT std_logic; LED_2 : OUT std_logic ); end ethernet; architecture ethernet_arch of ethernet is COMPONENT eth_top PORT( wb_clk_i : IN std_logic; wb_rst_i : IN std_logic; wb_dat_i : IN std_logic_vector(31 downto 0); wb_adr_i : IN std_logic_vector(11 downto 2); wb_sel_i : IN std_logic_vector(3 downto 0); wb_we_i : IN std_logic; wb_cyc_i : IN std_logic; wb_stb_i : IN std_logic; m_wb_dat_i : IN std_logic_vector(31 downto 0); m_wb_ack_i : IN std_logic; m_wb_err_i : IN std_logic; mtx_clk_pad_i : IN std_logic; mrx_clk_pad_i : IN std_logic; mrxd_pad_i : IN std_logic_vector(3 downto 0); mrxdv_pad_i : IN std_logic; mrxerr_pad_i : IN std_logic; mcoll_pad_i : IN std_logic; mcrs_pad_i : IN std_logic; md_pad_i : IN std_logic; wb_dat_o : OUT std_logic_vector(31 downto 0); wb_ack_o : OUT std_logic; wb_err_o : OUT std_logic; m_wb_adr_o : OUT std_logic_vector(31 downto 0); m_wb_sel_o : OUT std_logic_vector(3 downto 0); m_wb_we_o : OUT std_logic; m_wb_dat_o : OUT std_logic_vector(31 downto 0); m_wb_cyc_o : OUT std_logic; m_wb_stb_o : OUT std_logic; mtxd_pad_o : OUT std_logic_vector(3 downto 0); mtxen_pad_o : OUT std_logic; mtxerr_pad_o : OUT std_logic; mdc_pad_o : OUT std_logic; md_pad_o : OUT std_logic; md_padoe_o : OUT std_logic; m_wb_cti_o : OUT std_logic_vector(2 downto 0); m_wb_bte_o : OUT std_logic_vector(1 downto 0); int_o : OUT std_logic ); END COMPONENT; COMPONENT pci_bridge32 PORT( wb_clk_i : IN std_logic; wb_rst_i : IN std_logic; wb_int_i : IN std_logic; wbs_adr_i : IN std_logic_vector(31 downto 0); wbs_dat_i : IN std_logic_vector(31 downto 0); wbs_sel_i : IN std_logic_vector(3 downto 0); wbs_cyc_i : IN std_logic; wbs_stb_i : IN std_logic; wbs_we_i : IN std_logic; wbs_cti_i : IN std_logic_vector(2 downto 0); wbs_bte_i : IN std_logic_vector(1 downto 0); wbm_dat_i : IN std_logic_vector(31 downto 0); wbm_ack_i : IN std_logic; wbm_rty_i : IN std_logic; wbm_err_i : IN std_logic; pci_clk_i : IN std_logic; pci_rst_i : IN std_logic; pci_inta_i : IN std_logic; pci_gnt_i : IN std_logic; pci_frame_i : IN std_logic; pci_irdy_i : IN std_logic; pci_idsel_i : IN std_logic; pci_devsel_i : IN std_logic; pci_trdy_i : IN std_logic; pci_stop_i : IN std_logic; pci_ad_i : IN std_logic_vector(31 downto 0); pci_cbe_i : IN std_logic_vector(3 downto 0); pci_par_i : IN std_logic; pci_perr_i : IN std_logic; wb_rst_o : OUT std_logic; wb_int_o : OUT std_logic; wbs_dat_o : OUT std_logic_vector(31 downto 0); wbs_ack_o : OUT std_logic; wbs_rty_o : OUT std_logic; wbs_err_o : OUT std_logic; wbm_adr_o : OUT std_logic_vector(31 downto 0); wbm_dat_o : OUT std_logic_vector(31 downto 0); wbm_sel_o : OUT std_logic_vector(3 downto 0); wbm_cyc_o : OUT std_logic; wbm_stb_o : OUT std_logic; wbm_we_o : OUT std_logic; wbm_cti_o : OUT std_logic_vector(2 downto 0); wbm_bte_o : OUT std_logic_vector(1 downto 0); pci_rst_o : OUT std_logic; pci_inta_o : OUT std_logic; pci_rst_oe_o : OUT std_logic; pci_inta_oe_o : OUT std_logic; pci_req_o : OUT std_logic; pci_req_oe_o : OUT std_logic; pci_frame_o : OUT std_logic; pci_frame_oe_o : OUT std_logic; pci_irdy_oe_o : OUT std_logic; pci_devsel_oe_o : OUT std_logic; pci_trdy_oe_o : OUT std_logic; pci_stop_oe_o : OUT std_logic; pci_ad_oe_o : OUT std_logic_vector(31 downto 0); pci_cbe_oe_o : OUT std_logic_vector(3 downto 0); pci_irdy_o : OUT std_logic; pci_devsel_o : OUT std_logic; pci_trdy_o : OUT std_logic; pci_stop_o : OUT std_logic; pci_ad_o : OUT std_logic_vector(31 downto 0); pci_cbe_o : OUT std_logic_vector(3 downto 0); pci_par_o : OUT std_logic; pci_par_oe_o : OUT std_logic; pci_perr_o : OUT std_logic; pci_perr_oe_o : OUT std_logic; pci_serr_o : OUT std_logic; pci_serr_oe_o : OUT std_logic ); END COMPONENT; component icon port ( control0 : out std_logic_vector(35 downto 0) ); end component; component ila port ( control : in std_logic_vector(35 downto 0); clk : in std_logic; data : in std_logic_vector(63 downto 0); trig0 : in std_logic_vector(31 downto 0) ); end component; component phydcm is port ( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLKFX_OUT : out std_logic; CLK0_OUT : out std_logic; LOCKED_OUT : out std_logic); end component; signal pci_rst_i : std_logic; signal pci_rst_o : std_logic; signal pci_rst_oe_o : std_logic; signal pci_inta_i : std_logic; signal pci_inta_o : std_logic; signal pci_inta_oe_o : std_logic; signal pci_req_o : std_logic; signal pci_req_oe_o : std_logic; signal pci_frame_i : std_logic; signal pci_frame_o : std_logic; signal pci_frame_oe_o : std_logic; signal pci_irdy_i : std_logic; signal pci_irdy_o : std_logic; signal pci_irdy_oe_o : std_logic; signal pci_devsel_i : std_logic; signal pci_devsel_o : std_logic; signal pci_devsel_oe_o : std_logic; signal pci_trdy_i : std_logic; signal pci_trdy_o : std_logic; signal pci_trdy_oe_o : std_logic; signal pci_stop_i : std_logic; signal pci_stop_o : std_logic; signal pci_stop_oe_o : std_logic; signal pci_par_i : std_logic; signal pci_par_o : std_logic; signal pci_par_oe_o : std_logic; signal pci_perr_i : std_logic; signal pci_perr_o : std_logic; signal pci_perr_oe_o : std_logic; signal pci_serr_i : std_logic; signal pci_serr_o : std_logic; signal pci_serr_oe_o : std_logic; signal pci_ad_oe_o : std_logic_vector(31 downto 0); signal pci_cbe_oe_o : std_logic_vector(3 downto 0); signal pci_ad_i : std_logic_vector (31 downto 0); signal pci_ad_o : std_logic_vector (31 downto 0); signal pci_cbe_i : std_logic_vector (3 downto 0); signal pci_cbe_o : std_logic_vector (3 downto 0); signal wb_clk_i : std_logic; signal wb_rst_i : std_logic; signal wb_dat_i : std_logic_vector (31 downto 0); signal wb_dat_o : std_logic_vector (31 downto 0); signal wb_adr_i : std_logic_vector (11 downto 2); signal wb_sel_i : std_logic_vector (3 downto 0); signal wb_we_i : std_logic; signal wb_cyc_i : std_logic; signal wb_stb_i : std_logic; signal wb_ack_o : std_logic; signal wb_err_o : std_logic; signal m_wb_adr_o : std_logic_vector(31 downto 0); signal m_wb_sel_o : std_logic_vector(3 downto 0); signal m_wb_we_o : std_logic; signal m_wb_dat_o : std_logic_vector(31 downto 0); signal m_wb_dat_i : std_logic_vector(31 downto 0); signal m_wb_cyc_o : std_logic; signal m_wb_stb_o : std_logic; signal m_wb_ack_i : std_logic; signal m_wb_err_i : std_logic; signal md_pad_i : std_logic; signal md_pad_o : std_logic; signal md_padoe_o : std_logic; signal int_o : std_logic; signal wbm_adr_o : std_logic_vector(31 downto 0); signal mdc_pad_o_watch : std_logic; signal m_wb_cti_o : std_logic_vector(2 downto 0); signal m_wb_bte_o : std_logic_vector(1 downto 0); signal control0 : std_logic_vector(35 downto 0); signal data : std_logic_vector(63 downto 0); signal trig0 : std_logic_vector(31 downto 0); BEGIN IOBUF_PCI_RSTn: IOBUF port map ( IO => PCI_RSTn, T => pci_rst_oe_o, I => pci_rst_o, O => pci_rst_i ); IOBUF_PCI_INTAn: IOBUF port map ( IO => PCI_INTAn, T => pci_inta_oe_o, I => pci_inta_o, O => pci_inta_i ); OBUFT_PCI_REQn: OBUFT port map ( O => PCI_REQn, T => pci_req_oe_o, I => pci_req_o ); IOBUF_PCI_FRAMEn: IOBUF port map ( IO => PCI_FRAMEn, T => pci_frame_oe_o, I => pci_frame_o, O => pci_frame_i ); IOBUF_PCI_IRDYn: IOBUF port map ( IO => PCI_IRDYn, T => pci_irdy_oe_o, I => pci_irdy_o, O => pci_irdy_i ); IOBUF_PCI_DEVSELn: IOBUF port map ( IO => PCI_DEVSELn, T => pci_devsel_oe_o, I => pci_devsel_o, O => pci_devsel_i ); IOBUF_PCI_TRDYn: IOBUF port map ( IO => PCI_TRDYn, T => pci_trdy_oe_o, I => pci_trdy_o, O => pci_trdy_i ); IOBUF_PCI_STOPn: IOBUF port map ( IO => PCI_STOPn, T => pci_stop_oe_o, I => pci_stop_o, O => pci_stop_i ); IOBUF_PCI_PAR: IOBUF port map ( IO => PCI_PAR, T => pci_par_oe_o, I => pci_par_o, O => pci_par_i ); IOBUF_PCI_PERRn: IOBUF port map ( IO => PCI_PERRn, T => pci_perr_oe_o, I => pci_perr_o, O => pci_perr_i ); IOBUF_PCI_SERRn: IOBUF port map ( IO => PCI_SERRn, T => pci_serr_oe_o, I => pci_serr_o, O => pci_serr_i ); IOBUF_MD_PAD_IO: IOBUF port map ( IO => MD_PAD_IO, T => md_padoe_o, I => md_pad_o, O => md_pad_i ); BLA1: FOR i in 31 downto 0 generate IOBUF_PCI_AD: IOBUF port map ( IO => PCI_AD(i), T => pci_ad_oe_o(i), I => pci_ad_o(i), O => pci_ad_i(i) ); end generate; BLA2: FOR i in 3 downto 0 generate IOBUF_PCI_CBEn: IOBUF port map ( IO => PCI_CBEn(i), T => pci_cbe_oe_o(i), I => pci_cbe_o(i), O => pci_cbe_i(i) ); end generate; wb_adr_i(11 downto 8) <= (others => '0'); wb_adr_i(7 downto 2) <= wbm_adr_o (7 downto 2); wb_clk_i <= PCI_CLOCK; data(31 downto 0) <= wbm_adr_o; data(39 downto 32) <= wbm_adr_o (7 downto 0); data(40) <= md_pad_i; data(41) <= md_pad_o; data(42) <= md_padoe_o; data(43) <= mdc_pad_o_watch; data(44) <= pci_inta_o; data(63 downto 45) <= (others => '0'); MDC_PAD_O <= mdc_pad_o_watch; trig0(31 downto 0) <= ( 0 => wb_stb_i, 1 => md_pad_i, 2 => md_pad_o, 3 => md_padoe_o, others => '0' ); Inst_pci_bridge32: pci_bridge32 PORT MAP( wb_clk_i => wb_clk_i , wb_rst_i => '0', wb_rst_o => wb_rst_i, wb_int_i => int_o, -- wb_int_o => , wbs_adr_i => m_wb_adr_o , wbs_dat_i => m_wb_dat_o, wbs_dat_o => m_wb_dat_i, wbs_sel_i => m_wb_sel_o, wbs_cyc_i => m_wb_cyc_o, wbs_stb_i => m_wb_stb_o, wbs_we_i => m_wb_we_o, wbs_cti_i => m_wb_cti_o, wbs_bte_i => m_wb_bte_o, wbs_ack_o => m_wb_ack_i, -- wbs_rty_o => , wbs_err_o => m_wb_err_i, wbm_adr_o => wbm_adr_o, wbm_dat_i => wb_dat_o, wbm_dat_o => wb_dat_i, wbm_sel_o => wb_sel_i, wbm_cyc_o => wb_cyc_i, wbm_stb_o => wb_stb_i, wbm_we_o => wb_we_i, -- wbm_cti_o => , -- wbm_bte_o => , wbm_ack_i => wb_ack_o , wbm_rty_i => '0', wbm_err_i => wb_err_o, pci_clk_i => PCI_CLOCK, pci_rst_i => pci_rst_i, pci_rst_o => pci_rst_o , pci_rst_oe_o => pci_rst_oe_o, pci_inta_i => pci_inta_i, pci_inta_o => pci_inta_o, pci_inta_oe_o => pci_inta_oe_o, pci_req_o => pci_req_o, pci_req_oe_o => pci_req_oe_o, pci_gnt_i => PCI_GNTn, pci_frame_i => pci_frame_i, pci_frame_o => pci_frame_o, pci_frame_oe_o => pci_frame_oe_o, pci_irdy_oe_o => pci_irdy_oe_o, pci_devsel_oe_o => pci_devsel_oe_o, pci_trdy_oe_o => pci_trdy_oe_o, pci_stop_oe_o => pci_stop_oe_o, pci_ad_oe_o => pci_ad_oe_o, pci_cbe_oe_o => pci_cbe_oe_o, pci_irdy_i => pci_irdy_i, pci_irdy_o => pci_irdy_o, pci_idsel_i => PCI_IDSEL, pci_devsel_i => pci_devsel_i, pci_devsel_o => pci_devsel_o, pci_trdy_i => pci_trdy_i, pci_trdy_o => pci_trdy_o, pci_stop_i => pci_stop_i, pci_stop_o => pci_stop_o, pci_ad_i => pci_ad_i, pci_ad_o => pci_ad_o, pci_cbe_i => pci_cbe_i, pci_cbe_o => pci_cbe_o, pci_par_i => pci_par_i, pci_par_o => pci_par_o, pci_par_oe_o => pci_par_oe_o, pci_perr_i => pci_perr_i, pci_perr_o => pci_perr_o, pci_perr_oe_o => pci_perr_oe_o, pci_serr_o => pci_serr_o, pci_serr_oe_o => pci_serr_oe_o ); Inst_eth_top: eth_top PORT MAP( wb_clk_i => wb_clk_i , wb_rst_i => wb_rst_i , wb_dat_i => wb_dat_i , wb_dat_o => wb_dat_o , wb_adr_i => wb_adr_i , wb_sel_i => wb_sel_i , wb_we_i => wb_we_i , wb_cyc_i => wb_cyc_i , wb_stb_i => wb_stb_i, wb_ack_o => wb_ack_o , wb_err_o => wb_err_o , m_wb_adr_o => m_wb_adr_o, m_wb_sel_o => m_wb_sel_o, m_wb_we_o => m_wb_we_o , m_wb_dat_o => m_wb_dat_o, m_wb_dat_i => m_wb_dat_i, m_wb_cyc_o => m_wb_cyc_o, m_wb_stb_o => m_wb_stb_o, m_wb_ack_i => m_wb_ack_i, m_wb_err_i => m_wb_err_i, mtx_clk_pad_i => MTX_CLK_PAD_I, mtxd_pad_o => MTXD_PAD_O, mtxen_pad_o => MTXEN_PAD_O, mtxerr_pad_o => LED_2, mrx_clk_pad_i => MRX_CLK_PAD_I, mrxd_pad_i => MRXD_PAD_I, mrxdv_pad_i => MRXDV_PAD_I, mrxerr_pad_i => MRXERR_PAD_I, mcoll_pad_i => MCOLL_PAD_I, mcrs_pad_i => MCRS_PAD_I, mdc_pad_o => mdc_pad_o_watch, md_pad_i => md_pad_i, md_pad_o => md_pad_o, md_padoe_o => md_padoe_o, m_wb_cti_o => m_wb_cti_o, m_wb_bte_o => m_wb_bte_o, int_o => int_o ); i_icon : icon port map ( control0 => control0 ); i_ila : ila port map ( control => control0, clk => PCI_CLOCK, data => data, trig0 => trig0 ); eth_dcm : phydcm port map ( CLKIN_IN => PCI_CLOCK, RST_IN => not pci_rst_i, CLKFX_OUT => PHY_CLOCK, CLK0_OUT => open, LOCKED_OUT => open ); end architecture ethernet_arch;