---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 22:50:29 03/05/2007 -- Design Name: -- Module Name: ide - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity ide is Port ( LED_1 : out STD_LOGIC; LED_2 : out STD_LOGIC; LED_3 : out STD_LOGIC; LED_4 : out STD_LOGIC; IDE_DATA : out std_logic_vector(15 downto 0); IDE_ADDR : out std_logic_vector(2 downto 0); IDE_RESET : out std_logic; IDE_IO_READ : out std_logic; IDE_GPIO_DMA66_DETECT : out std_logic; IDE_DDRQ : out std_logic; IDE_CABLE_SELECT : out std_logic; IDE_IO_WRITE : out std_logic; IDE_IOC_HRDY : out std_logic; IDE_DDACK : out std_logic; IDE_CHIP_SELECT_1P : out std_logic; IDE_CHIP_SELECT_3P : out std_logic; IDE_IRQ : out std_logic; IDE_ACTIVITY : out std_logic; FPGA1 : in std_logic; FPGA2 : in std_logic; FPGA3 : in std_logic; FPGA4 : in std_logic; FPGA5 : out std_logic; FPGA6 : out std_logic; FPGA7 : out std_logic; FPGA8 : out std_logic; FPGA9 : out std_logic; FPGA10 : out std_logic; FPGA11 : out std_logic; FPGA12 : out std_logic; FPGA13 : out std_logic; FPGA14 : out std_logic; FPGA15 : out std_logic; FPGA16 : out std_logic; OUT1 : out std_logic; OUT2 : out std_logic; OUT3 : out std_logic; OUT4 : out std_logic; OUT5 : out std_logic; OUT6 : out std_logic; OUT7 : out std_logic; OUT8 : out std_logic; OUT9 : out std_logic; OUT10 : out std_logic; OUT11 : out std_logic; OUT12 : out std_logic; OUT13 : out std_logic; OUT14 : out std_logic; OUT15 : out std_logic; OUT16 : out std_logic; OUT17 : out std_logic; OUT18 : out std_logic; OUT19 : out std_logic; OUT20 : out std_logic ); end ide; architecture Behavioral of ide is begin LED_1 <= FPGA1; LED_2 <= FPGA2; LED_3 <= FPGA3; LED_4 <= FPGA4; end Behavioral;