# BEGIN Project Options SET addpads = False SET asysymbol = False SET busformat = BusFormatAngleBracketNotRipped SET createndf = False SET designentry = VHDL SET device = xc3s1500 SET devicefamily = spartan3 SET flowvendor = Other SET formalverification = False SET foundationsym = False SET implementationfiletype = Ngc SET package = fg456 SET removerpms = False SET simulationfiles = Structural SET speedgrade = -4 SET verilogsim = False SET vhdlsim = True # END Project Options # BEGIN Select SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.02.a # END Select # BEGIN Parameters CSET component_name=icon CSET number_control_ports=1 CSET use_ext_bscan=false CSET use_jtag_bufg=false CSET use_unused_bscan=false CSET user_scan_chain=USER1 # END Parameters GENERATE