module wb_fifo (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, fifo_data_i, fifo_data_o, fifo_we_o, fifo_re_o); input clk_i; input nrst_i; input [24:1] wb_adr_i; output [15:0] wb_dat_o; input [15:0] wb_dat_i; input [1:0] wb_sel_i; input wb_we_i; input wb_stb_i; input wb_cyc_i; output wb_ack_o; output wb_err_o; output wb_int_o; input [7:0] fifo_data_i; output [7:0] fifo_data_o; output fifo_we_o; output fifo_re_o; reg [15:0] data_reg; always @(posedge clk_i or negedge nrst_i) begin if (nrst_i == 0) data_reg <= 16'h0000; else if (wb_stb_i && wb_we_i) data_reg <= wb_dat_i; end assign fifo_we_o = 1'b1; assign fifo_data_o = data_reg; assign wb_ack_o = wb_stb_i; assign wb_err_o = 1'b0; assign wb_int_o = 1'b0; assign wb_dat_o = data_reg; endmodule