rename fifo to dhwk_fifo

[raggedstone] / dhwk / source / top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 84f04dd95724c2b9c0280da536dbef1236ba1228..bf927d84931e93850197a826d2207a781a7f31c1 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -209,7 +209,7 @@ architecture SCHEMATIC of dhwk is
              WRITE_XX7_6 : Out   std_logic );\r
    end component;\r
 \r
              WRITE_XX7_6 : Out   std_logic );\r
    end component;\r
 \r

-component fifo_generator_v3_2\r
+component dhwk_fifo\r

         port (\r
         clk: IN std_logic;\r
         din: IN std_logic_VECTOR(7 downto 0);\r
         port (\r
         clk: IN std_logic;\r
         din: IN std_logic_VECTOR(7 downto 0);\r


@@ -364,7 +364,7 @@ begin
                  WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
                  WRITE_XX7_6=>WRITE_XX7_6 );\r
 \r
                  WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
                  WRITE_XX7_6=>WRITE_XX7_6 );\r
 \r

-receive_fifo : fifo_generator_v3_2\r
+receive_fifo : dhwk_fifo\r

                 port map (\r
                         clk => PCI_CLOCK,\r
                         din => R_FIFO_D_IN,\r
                 port map (\r
                         clk => PCI_CLOCK,\r
                         din => R_FIFO_D_IN,\r


@@ -376,7 +376,7 @@ receive_fifo : fifo_generator_v3_2
                         full => R_FFn,\r
                         prog_full => R_HFn);\r
 \r
                         full => R_FFn,\r
                         prog_full => R_HFn);\r
 \r

-send_fifo : fifo_generator_v3_2\r
+send_fifo : dhwk_fifo\r

                 port map (\r
                         clk => PCI_CLOCK,\r
                         din => S_FIFO_D_IN,\r
                 port map (\r
                         clk => PCI_CLOCK,\r
                         din => S_FIFO_D_IN,\r