irgendwie gehts

[raggedstone] / dhwk / source / fifo_control.vhd

diff --git a/dhwk/source/fifo_control.vhd b/dhwk/source/fifo_control.vhd
index 1c2d52ea88c3bf00fc17e17e78b10958c20862b2..9a934046a5d88c7ba0e9a623724d37160c2befbe 100644 (file)
--- a/dhwk/source/fifo_control.vhd
+++ b/dhwk/source/fifo_control.vhd
@@ -44,7 +44,8 @@ entity FIFO_CONTROL is
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r
              SYNC_FLAG : Out   std_logic_vector (7 downto 0);\r
-            PAR_SER_IN : Out std_logic_vector (7 downto 0));\r
+            PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
+            SER_PAR_OUT : Out std_logic_vector (7 downto 0));\r
 end FIFO_CONTROL;\r
 \r
 architecture SCHEMATIC of FIFO_CONTROL is\r
@@ -56,6 +57,7 @@ architecture SCHEMATIC of FIFO_CONTROL is
    signal XXXS_FIFO_READn : std_logic;\r
    signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);\r
    signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);\r
+   signal watcher : std_logic_vector (7 downto 0);\r
 \r
    component SER_PAR_CON\r
       Port ( PCI_CLOCK : In    std_logic;\r
@@ -129,14 +131,15 @@ begin
 \r
    SYNC_FLAG <= SYNC_FLAG_DUMMY;\r
    PAR_SER_IN <= S_FIFO_Q_OUT;\r
-\r
+   SER_PAR_OUT <= watcher;\r
+   R_FIFO_D_IN(7 downto 0) <= watcher;\r
 \r
    RESERVE <= gnd;\r
    I23 : SER_PAR_CON\r
       Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
                  SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,\r
                  SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
-                 PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
+                 PAR_OUT(7 downto 0)=>watcher,\r
                  R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );\r
    I22 : PAR_SER_CON\r
       Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r