irgendwie gehts

[raggedstone] / dhwk / source / top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index e2f307c0e6266ff027978c13b07d9ba352ff5594..2d25fcd56fbfd04c0d1db0c626379d5b2d7ba114 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -170,6 +170,7 @@ architecture SCHEMATIC of dhwk is
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r
             PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
              SPC_RDY_OUT : Out   std_logic;\r
              SR_ERROR : Out   std_logic;\r
             PAR_SER_IN : Out std_logic_vector (7 downto 0);\r

+            SER_PAR_OUT : Out std_logic_vector (7 downto 0);\r

              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
    end component;\r
 \r
              SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
    end component;\r
 \r


@@ -251,7 +252,7 @@ begin
        LED_4 <= '0';\r
        LED_5 <= not watch;\r
        PCI_INTAn <= watch;\r
        LED_4 <= '0';\r
        LED_5 <= not watch;\r
        PCI_INTAn <= watch;\r

-       trig0(7 downto 0) <= (0 => watch, others => '0');\r
+       trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r

        data(0) <= watch;\r
        \r
        data(1) <= R_EFn;\r
        data(0) <= watch;\r
        \r
        data(1) <= R_EFn;\r


@@ -272,6 +273,7 @@ begin
        data(16) <= SPC_RDY_IN;\r
        data(17) <= SERIAL_OUT;\r
        data(18) <= SPC_RDY_OUT;\r
        data(16) <= SPC_RDY_IN;\r
        data(17) <= SERIAL_OUT;\r
        data(18) <= SPC_RDY_OUT;\r

+       data(34 downto 27) <= R_FIFO_Q_OUT;\r

 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r