all files to lowercase,

[raggedstone] / dhwk / source / pci / ven_rev_id.vhd

diff --git a/dhwk/source/pci/ven_rev_id.vhd b/dhwk/source/pci/ven_rev_id.vhd
new file mode 100644 (file)
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+++ b/dhwk/source/pci/ven_rev_id.vhd
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+-- J.STELZNER
+-- INFORMATIK-3 LABOR
+-- 23.08.2006
+-- File: VEN_REV_ID.VHD
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity VEN_REV_ID is
+        port
+        (
+                VEN_ID :out std_logic_vector(15 downto 0);
+                REV_ID :out std_logic_vector( 7 downto 0)
+        );
+end entity VEN_REV_ID;
+
+architecture VEN_REV_ID_DESIGN of VEN_REV_ID is
+
+begin
+
+        VEN_ID <= X"2222";
+        REV_ID <= X"01";
+
+end architecture VEN_REV_ID_DESIGN;