perl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1'/rising_edge(PCI_CLOCK)/" *.vhd

[raggedstone] / dhwk / source / par_ser_con.vhd

diff --git a/dhwk/source/par_ser_con.vhd b/dhwk/source/par_ser_con.vhd
index 1c366e28f42f4560fd46c6cd389c43cce186f0c3..155bb2729077b6a092582ab5f98317acd5e27b51 100644 (file)
--- a/dhwk/source/par_ser_con.vhd
+++ b/dhwk/source/par_ser_con.vhd
@@ -1,4 +1,4 @@
--- $Id: par_ser_con.vhd,v 1.1 2007-03-11 08:55:29 sithglan Exp $
+-- $Id: par_ser_con.vhd,v 1.2 2007-03-11 09:14:58 sithglan Exp $

 
 library ieee;
 use ieee.std_logic_1164.all;
 
 library ieee;
 use ieee.std_logic_1164.all;


@@ -43,7 +43,7 @@ begin
 
         process(PCI_CLOCK)
         begin
 
         process(PCI_CLOCK)
         begin

-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then

                         if ("0000" < COUNT) then
                                 COUNT <= COUNT - 1;
                         end if;
                         if ("0000" < COUNT) then
                                 COUNT <= COUNT - 1;
                         end if;


@@ -115,7 +115,7 @@ begin
 
         process(PCI_CLOCK)
         begin
 
         process(PCI_CLOCK)
         begin

-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then

                         SYNC <= SPC_RDY_IN;
                 end if;
         end process;
                         SYNC <= SPC_RDY_IN;
                 end if;
         end process;