old 7seg thingie

[raggedstone] / dhwk_old / source / top_dhwk.vhd

diff --git a/dhwk_old/source/top_dhwk.vhd b/dhwk_old/source/top_dhwk.vhd
index 67fe5aa843739e8623d6436af03114a27d43a196..accd1a382677ce6d91bcf022783c6b4c6f212d41 100644 (file)
--- a/dhwk_old/source/top_dhwk.vhd
+++ b/dhwk_old/source/top_dhwk.vhd
@@ -109,34 +109,37 @@ port (
 );\r
 end component;\r
 \r
-component generic_dpram\r
+component wb_7seg_new\r
 port (\r
-       rclk            : in std_logic;\r
-       rrst            : in std_logic;\r
-       rce             : in std_logic;\r
-       oe              : in std_logic;\r
-       raddr           : in std_logic_vector(11 downto 0);\r
-       do              : out std_logic_vector(7 downto 0);\r
-       wclk            : in std_logic;\r
-       wrst            : in std_logic;\r
-       wce             : in std_logic;\r
-       we              : in std_logic;\r
-       waddr           : in std_logic_vector(11 downto 0);\r
-       di              : in std_logic_vector(7 downto 0)\r
+       clk_i           : in std_logic;\r
+       nrst_i          : in std_logic;\r
+       \r
+       wb_adr_i        : in std_logic_vector(24 downto 1);\r
+       wb_dat_o        : out std_logic_vector(15 downto 0);\r
+       wb_dat_i        : in std_logic_vector(15 downto 0);\r
+       wb_sel_i        : in std_logic_vector(1 downto 0);\r
+       wb_we_i         : in std_logic;\r
+       wb_stb_i        : in std_logic;\r
+       wb_cyc_i        : in std_logic;\r
+       wb_ack_o        : out std_logic;\r
+       wb_err_o        : out std_logic;\r
+       wb_int_o        : out std_logic;\r
+       \r
+       DISP_SEL        : inout std_logic_vector(3 downto 0);\r
+       DISP_LED        : out std_logic_vector(6 downto 0)\r
 );\r
 end component;\r
 \r
-\r
-       signal  wb_adr :                std_logic_vector(24 downto 1);   \r
-       signal  wb_dat_out :    std_logic_vector(15 downto 0);\r
-       signal  wb_dat_in :             std_logic_vector(15 downto 0);\r
-       signal  wb_sel :                std_logic_vector(1 downto 0);\r
-       signal  wb_we :                 std_logic;\r
-       signal  wb_stb :                std_logic;\r
-       signal  wb_cyc :                std_logic;\r
-       signal  wb_ack :                std_logic;\r
-       signal  wb_err :                std_logic;\r
-       signal  wb_int :                std_logic;\r
+signal         wb_adr :                std_logic_vector(24 downto 1);   \r
+signal wb_dat_out :    std_logic_vector(15 downto 0);\r
+signal         wb_dat_in :             std_logic_vector(15 downto 0);\r
+signal wb_sel :                std_logic_vector(1 downto 0);\r
+signal  wb_we :                        std_logic;\r
+signal wb_stb :                std_logic;\r
+signal wb_cyc :                std_logic;\r
+signal wb_ack :                std_logic;\r
+signal wb_err :                std_logic;\r
+signal wb_int :                std_logic;\r
 \r
 \r
 begin\r