add PCI_nREQ

[raggedstone] / heartbeat / source / top_raggedstone.vhd

diff --git a/heartbeat/source/top_raggedstone.vhd b/heartbeat/source/top_raggedstone.vhd
index 73fefb15d8298f6eaf34a6a9804a2b87ba067da8..3d369cf5dae28104afb9dd4d3cf51a7dc1c2cd01 100644 (file)
--- a/heartbeat/source/top_raggedstone.vhd
+++ b/heartbeat/source/top_raggedstone.vhd
@@ -38,12 +38,13 @@ use ieee.std_logic_unsigned.all;
 --|                                                                    ENTITY                                                                          |\r
 --+-----------------------------------------------------------------------------+\r
 \r
-entity pci_7seg is\r
+entity raggedstone is\r
 port (\r
 \r
     -- General \r
     PCI_CLK     : in std_logic;\r
     PCI_nRES    : in std_logic;\r
+    PCI_nREQ    : out std_logic;\r
     \r
     -- PCI target 32bits\r
     PCI_AD      : inout std_logic_vector(31 downto 0);\r
@@ -60,19 +61,24 @@ port (
     PCI_nINT    : out std_logic;\r
  \r
        -- debug signals\r
-       LED_INIT         : out std_logic;\r
-       LED_ACCESS       : out std_logic;\r
-       LED_ALIVE : out std_logic\r
+       LED3    : out std_logic;\r
+       LED2    : out std_logic;\r
+       LED4            : out std_logic;\r
+       LED5            : out std_logic;\r
+       IDE1    : out std_logic;\r
+       IDE2    : out std_logic;\r
+       IDE3    : out std_logic;\r
+       IDE4    : out std_logic\r
 \r
 );\r
-end pci_7seg;\r
+end raggedstone;\r
 \r
 \r
 --+-----------------------------------------------------------------------------+\r
 --|                                                                    ARCHITECTURE                                                            |\r
 --+-----------------------------------------------------------------------------+\r
 \r
-architecture pci_7seg_arch of pci_7seg is\r
+architecture raggedstone_arch of raggedstone is\r
 \r
 \r
 --+-----------------------------------------------------------------------------+\r
@@ -123,7 +129,14 @@ component heartbeat
 port (\r
        clk_i : in std_logic;\r
        nrst_i : in std_logic;\r
-       led_o : out std_logic\r
+       led2_o : out std_logic;\r
+       led3_o : out std_logic;\r
+       led4_o : out std_logic;\r
+       led5_o : out std_logic;\r
+       led6_o : out std_logic;\r
+       led7_o : out std_logic;\r
+       led8_o : out std_logic;\r
+       led9_o : out std_logic\r
 );\r
 end component;\r
 \r
@@ -149,6 +162,8 @@ end component;
 \r
 begin\r
 \r
+       PCI_nREQ <= '1';\r
+\r
 --+-----------------------------------------+\r
 --|  PCI Target                                                        |\r
 --+-----------------------------------------+\r
@@ -178,9 +193,9 @@ port map(
                wb_cyc_o =>             wb_cyc,\r
                wb_ack_i =>             wb_ack,\r
                wb_err_i =>             wb_err,\r
-               wb_int_i =>             wb_int,\r
-               debug_init =>   LED_INIT,\r
-               debug_access => LED_ACCESS\r
+               wb_int_i =>             wb_int\r
+--             debug_init =>   LED3,\r
+--             debug_access => LED2\r
                );\r
 \r
 --+-----------------------------------------+\r
@@ -191,7 +206,14 @@ my_heartbeat: component heartbeat
 port map( \r
        clk_i => PCI_CLK,\r
        nrst_i => PCI_nRES,\r
-       led_o => LED_ALIVE\r
+       led2_o => LED2,\r
+       led3_o => LED3,\r
+       led4_o => LED4,\r
+       led5_o => LED5,\r
+       led6_o => IDE1,\r
+       led7_o => IDE2,\r
+       led8_o => IDE3,\r
+       led9_o => IDE4\r
 );\r
 \r
-end pci_7seg_arch;\r
+end raggedstone_arch;\r