+= fifo

[raggedstone] / heartbeat / source / heartbeat.vhd

diff --git a/heartbeat/source/heartbeat.vhd b/heartbeat/source/heartbeat.vhd
index 76f084d8feaa4ce72a00a338ab68a53a184e2e6d..e079bbb5667dc41df3d35ed7bec0d471879327d1 100644 (file)
--- a/heartbeat/source/heartbeat.vhd
+++ b/heartbeat/source/heartbeat.vhd
@@ -5,13 +5,16 @@ use ieee.std_logic_unsigned.all;
 
 entity heartbeat is
 generic (
-       divider : integer := 33000000
+       divider : std_logic_vector(31 downto 0) := X"01F78A40"
 );
 
 port (
        clk_i : in std_logic;
        nrst_i : in std_logic;
-       led_o : out std_logic
+       led2_o : out std_logic;
+       led3_o : out std_logic;
+       led4_o : out std_logic;
+       led5_o : out std_logic
 );   
 
 end heartbeat;
@@ -28,10 +31,14 @@ if (clk_i'event AND clk_i = '1') then
        if nrst_i = '0' then
                counter := (others => '0');
         else
-               led_o <= state;
+               led5_o <= state;
+               led2_o <= state;
+               led4_o <= not state;
+               led3_o <= not state;
                counter := counter + 1;
                if counter = divider then
                        state := not state;
+                       counter := (others => '0');
                end if;
        end if;
 end if;