update to EDK 9.1i

[raggedstone] / ethernet / source / top.vhd

diff --git a/ethernet/source/top.vhd b/ethernet/source/top.vhd
index 05412220f19ed50fd14f1b5b09ab8f81af9f2867..f7c5bd9ad33f02ebb0793dfec585450362f210d8 100644 (file)
--- a/ethernet/source/top.vhd
+++ b/ethernet/source/top.vhd
@@ -30,7 +30,11 @@ PORT(
         MCOLL_PAD_I : IN std_logic;
         MCRS_PAD_I : IN std_logic;
         MD_PAD_IO : INOUT std_logic;
-        MDC_PAD_O : OUT std_logic
+        MDC_PAD_O : OUT std_logic;
+
+       PHY_CLOCK : OUT std_logic;
+
+       LED_2 : OUT std_logic
 );
 end ethernet;
 
@@ -72,6 +76,8 @@ PORT(
         mdc_pad_o : OUT std_logic;
         md_pad_o : OUT std_logic;
         md_padoe_o : OUT std_logic;
+        m_wb_cti_o : OUT std_logic_vector(2 downto 0);
+        m_wb_bte_o : OUT std_logic_vector(1 downto 0);
         int_o : OUT std_logic
         );
 END COMPONENT;
@@ -150,6 +156,29 @@ PORT(
         );
 END COMPONENT;
 
+component icon
+port (
+       control0 : out std_logic_vector(35 downto 0)
+       );
+end component;
+
+component ila
+port (
+       control : in std_logic_vector(35 downto 0);
+       clk : in std_logic;
+       data : in std_logic_vector(63 downto 0);
+       trig0 : in std_logic_vector(31 downto 0)
+       );
+end component;
+
+component phydcm is
+port ( CLKIN_IN        : in    std_logic;
+       RST_IN          : in    std_logic;
+       CLKFX_OUT       : out   std_logic;
+       CLK0_OUT        : out   std_logic;
+       LOCKED_OUT      : out   std_logic);
+end component;
+
 signal pci_rst_o : std_logic;
 signal pci_rst_oe_o : std_logic;
 signal pci_inta_o : std_logic;
@@ -201,6 +230,15 @@ signal md_pad_o : std_logic;
 signal md_padoe_o : std_logic;
 signal int_o : std_logic;
 signal wbm_adr_o : std_logic_vector(31 downto 0);
+signal mdc_pad_o_watch : std_logic;
+
+signal m_wb_cti_o : std_logic_vector(2 downto 0);
+signal m_wb_bte_o : std_logic_vector(1 downto 0);
+
+signal control0 : std_logic_vector(35 downto 0);
+signal data : std_logic_vector(63 downto 0);
+signal trig0 : std_logic_vector(31 downto 0);
+
 
 BEGIN
 
@@ -225,7 +263,28 @@ BLA2: FOR i in 3 downto 0 generate
 PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
 end generate;
 
-wb_adr_i <= wbm_adr_o (11 downto 2);
+wb_adr_i(11 downto 8) <= (others => '0');
+wb_adr_i(7 downto 2)  <= wbm_adr_o (7 downto 2);
+
+wb_clk_i <= PCI_CLOCK;
+
+data(31 downto 0)  <= wbm_adr_o;
+data(39 downto 32) <= wbm_adr_o (7 downto 0);
+data(40) <= MD_PAD_IO;
+data(41) <= md_pad_o;
+data(42) <= md_padoe_o;
+data(43) <= mdc_pad_o_watch;
+data(44) <= pci_inta_o;
+MDC_PAD_O <= mdc_pad_o_watch;
+data(63 downto 45) <= (others => '0');
+
+trig0(31 downto 0) <= (
+       0 => wb_stb_i,
+       1 => MD_PAD_IO,
+       2 => md_pad_o,
+       3 => md_padoe_o,
+       others => '0'
+);
 
 Inst_pci_bridge32: pci_bridge32 PORT MAP(
         wb_clk_i => wb_clk_i ,
@@ -240,8 +299,8 @@ Inst_pci_bridge32: pci_bridge32 PORT MAP(
         wbs_cyc_i => m_wb_cyc_o,
         wbs_stb_i => m_wb_stb_o,
         wbs_we_i => m_wb_we_o,
-        wbs_cti_i => (others => '0'),
-        wbs_bte_i => (others => '0'),
+        wbs_cti_i => m_wb_cti_o,
+        wbs_bte_i => m_wb_bte_o,
         wbs_ack_o => m_wb_ack_i,
         -- wbs_rty_o => ,
         wbs_err_o => m_wb_err_i,
@@ -308,7 +367,7 @@ Inst_eth_top: eth_top PORT MAP(
         wb_sel_i   => wb_sel_i  ,
         wb_we_i    => wb_we_i   ,
         wb_cyc_i   => wb_cyc_i  ,
-        wb_stb_i   => wb_stb_i  ,
+        wb_stb_i   => wb_stb_i,
         wb_ack_o   => wb_ack_o  ,
         wb_err_o   => wb_err_o  ,
         m_wb_adr_o => m_wb_adr_o,
@@ -323,18 +382,42 @@ Inst_eth_top: eth_top PORT MAP(
         mtx_clk_pad_i => MTX_CLK_PAD_I,
         mtxd_pad_o => MTXD_PAD_O,
         mtxen_pad_o => MTXEN_PAD_O,
-        -- mtxerr_pad_o => ,
+        mtxerr_pad_o => LED_2,
         mrx_clk_pad_i => MRX_CLK_PAD_I,
         mrxd_pad_i => MRXD_PAD_I,
         mrxdv_pad_i => MRXDV_PAD_I,
         mrxerr_pad_i => MRXERR_PAD_I,
         mcoll_pad_i => MCOLL_PAD_I,
         mcrs_pad_i => MCRS_PAD_I,
-        mdc_pad_o => MDC_PAD_O,
+        mdc_pad_o => mdc_pad_o_watch,
         md_pad_i => MD_PAD_IO,
         md_pad_o => md_pad_o,
         md_padoe_o => md_padoe_o,
+        m_wb_cti_o => m_wb_cti_o,
+        m_wb_bte_o => m_wb_bte_o, 
         int_o => int_o
 );
 
+i_icon : icon
+port map (
+       control0 => control0
+       );
+
+i_ila : ila
+port map (
+       control => control0,
+       clk => PCI_CLOCK,
+       data => data,
+       trig0 => trig0
+       );
+
+eth_dcm : phydcm
+port map (
+       CLKIN_IN => PCI_CLOCK,
+       RST_IN => not PCI_RSTn,
+       CLKFX_OUT => PHY_CLOCK,
+       CLK0_OUT => open,
+       LOCKED_OUT => open
+       );
+
 end architecture ethernet_arch;