Update ChipScope coregeneration to coregen as used in ISE Design Suite 10.1

[raggedstone] / dhwk / ila.arg

diff --git a/dhwk/ila.arg b/dhwk/ila.arg
deleted file mode 100644 (file)
index 2433cb4..0000000
--- a/dhwk/ila.arg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# Usage: generate.exe ila -f=<arg_file_name>
-#
--compname=ila
--outputdirectory=.
--datadepth=4096
--datawidth=96
--numtrigports=1
--trigportwidth0=32
--nummatchunits=1
--mtrigport0=0
--mtype0=0
--enablestoragequal
--devicefamily=Spartan3
--srl16type=2
--createcdc