Update ChipScope coregeneration to coregen as used in ISE Design Suite 10.1

[raggedstone] / dhwk / vio.arg

diff --git a/dhwk/vio.arg b/dhwk/vio.arg
deleted file mode 100644 (file)
index e719ad4..0000000
--- a/dhwk/vio.arg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Usage: generate.exe vio -f=<arg_file_name>
-#
--compname=vio
--outputdirectory=.
--devicefamily=Virtex4
--srl16type=2
--asyncinwidth=4
--syncoutwidth=1
--createcdc