Update ChipScope coregeneration to coregen as used in ISE Design Suite 10.1

[raggedstone] / ethernet / Makefile

diff --git a/ethernet/Makefile b/ethernet/Makefile
index 1569b23b79f1b5d9c7e601e37a618e630f0cb235..e8a70313a0133ab59e0899fb6c40250cf813bb4f 100644 (file)
--- a/ethernet/Makefile
+++ b/ethernet/Makefile
@@ -1,13 +1,16 @@
 PROJECT := ethernet
 PROJECT := ethernet

+CLEANFILES := param.opt icon.vhd icon.vho icon_flist.txt icon_readme.txt icon_xmdf.tcl ila.vhd ila.vho ila_flist.txt ila_readme.txt ila_xmdf.tcl

 
 ethernet_all: ip all
 
 
 ethernet_all: ip all
 

-ip: icon.edn ila.edn
+ip: icon.ngc ila.ngc

 
 

-icon.edn: icon.arg
-       $(CHIPSCOPE)/bin/lin/generate.sh icon -f=$<
+icon.ngc: icon.xco
+       coregen -b $<
+       -rmdir -p tmp/_cg

 
 

-ila.edn: ila.arg
-       $(CHIPSCOPE)/bin/lin/generate.sh ila -f=$<
+ila.ngc: ila.xco
+       coregen -b $<
+       -rmdir -p tmp/_cg

 
 include ../common/Makefile.common
 
 include ../common/Makefile.common