MCOLL_PAD_I : IN std_logic;
MCRS_PAD_I : IN std_logic;
MD_PAD_IO : INOUT std_logic;
- MDC_PAD_O : OUT std_logic
+ MDC_PAD_O : OUT std_logic;
+
+ LED_2 : OUT std_logic
);
end ethernet;
mdc_pad_o : OUT std_logic;
md_pad_o : OUT std_logic;
md_padoe_o : OUT std_logic;
+ m_wb_cti_o : OUT std_logic_vector(2 downto 0);
+ m_wb_bte_o : OUT std_logic_vector(1 downto 0);
int_o : OUT std_logic
);
END COMPONENT;
);
END COMPONENT;
+COMPONENT eth_cop
+PORT(
+ wb_clk_i : IN std_logic;
+ wb_rst_i : IN std_logic;
+ m1_wb_adr_i : IN std_logic_vector(31 downto 0);
+ m1_wb_sel_i : IN std_logic_vector(3 downto 0);
+ m1_wb_we_i : IN std_logic;
+ m1_wb_dat_i : IN std_logic_vector(31 downto 0);
+ m1_wb_cyc_i : IN std_logic;
+ m1_wb_stb_i : IN std_logic;
+ m2_wb_adr_i : IN std_logic_vector(31 downto 0);
+ m2_wb_sel_i : IN std_logic_vector(3 downto 0);
+ m2_wb_we_i : IN std_logic;
+ m2_wb_dat_i : IN std_logic_vector(31 downto 0);
+ m2_wb_cyc_i : IN std_logic;
+ m2_wb_stb_i : IN std_logic;
+ s1_wb_ack_i : IN std_logic;
+ s1_wb_err_i : IN std_logic;
+ s1_wb_dat_i : IN std_logic_vector(31 downto 0);
+ s2_wb_ack_i : IN std_logic;
+ s2_wb_err_i : IN std_logic;
+ s2_wb_dat_i : IN std_logic_vector(31 downto 0);
+ m1_wb_dat_o : OUT std_logic_vector(31 downto 0);
+ m1_wb_ack_o : OUT std_logic;
+ m1_wb_err_o : OUT std_logic;
+ m2_wb_dat_o : OUT std_logic_vector(31 downto 0);
+ m2_wb_ack_o : OUT std_logic;
+ m2_wb_err_o : OUT std_logic;
+ s1_wb_adr_o : OUT std_logic_vector(31 downto 0);
+ s1_wb_sel_o : OUT std_logic_vector(3 downto 0);
+ s1_wb_we_o : OUT std_logic;
+ s1_wb_cyc_o : OUT std_logic;
+ s1_wb_stb_o : OUT std_logic;
+ s1_wb_dat_o : OUT std_logic_vector(31 downto 0);
+ s2_wb_adr_o : OUT std_logic_vector(31 downto 0);
+ s2_wb_sel_o : OUT std_logic_vector(3 downto 0);
+ s2_wb_we_o : OUT std_logic;
+ s2_wb_cyc_o : OUT std_logic;
+ s2_wb_stb_o : OUT std_logic;
+ s2_wb_dat_o : OUT std_logic_vector(31 downto 0)
+ );
+END COMPONENT;
+
signal pci_rst_o : std_logic;
signal pci_rst_oe_o : std_logic;
signal pci_inta_o : std_logic;
signal int_o : std_logic;
signal wbm_adr_o : std_logic_vector(31 downto 0);
+signal m_wb_cti_o : std_logic_vector(2 downto 0);
+signal m_wb_bte_o : std_logic_vector(1 downto 0);
+
BEGIN
-PCI_RSTn <= not pci_rst_o when (pci_rst_oe_o = '1') else 'Z';
-PCI_INTAn <= not pci_inta_o when (pci_inta_oe_o = '1') else 'Z';
-PCI_REQn <= not pci_req_o when (pci_req_oe_o = '1') else 'Z';
-PCI_FRAMEn <= not pci_frame_o when (pci_frame_oe_o = '1') else 'Z';
-PCI_IRDYn <= not pci_irdy_o when (pci_irdy_oe_o = '1') else 'Z';
-PCI_DEVSELn <= not pci_devsel_o when (pci_devsel_oe_o = '1') else 'Z';
-PCI_TRDYn <= not pci_trdy_o when (pci_trdy_oe_o = '1') else 'Z';
-PCI_STOPn <= not pci_stop_o when (pci_stop_oe_o = '1') else 'Z';
+PCI_RSTn <= pci_rst_o when (pci_rst_oe_o = '1') else 'Z';
+PCI_INTAn <= pci_inta_o when (pci_inta_oe_o = '1') else 'Z';
+PCI_REQn <= pci_req_o when (pci_req_oe_o = '1') else 'Z';
+PCI_FRAMEn <= pci_frame_o when (pci_frame_oe_o = '1') else 'Z';
+PCI_IRDYn <= pci_irdy_o when (pci_irdy_oe_o = '1') else 'Z';
+PCI_DEVSELn <= pci_devsel_o when (pci_devsel_oe_o = '1') else 'Z';
+PCI_TRDYn <= pci_trdy_o when (pci_trdy_oe_o = '1') else 'Z';
+PCI_STOPn <= pci_stop_o when (pci_stop_oe_o = '1') else 'Z';
PCI_PAR <= pci_par_o when (pci_par_oe_o = '1') else 'Z';
-PCI_PERRn <= not pci_perr_o when (pci_perr_oe_o = '1') else 'Z';
-PCI_SERRn <= not pci_serr_o when (pci_serr_oe_o = '1') else 'Z';
+PCI_PERRn <= pci_perr_o when (pci_perr_oe_o = '1') else 'Z';
+PCI_SERRn <= pci_serr_o when (pci_serr_oe_o = '1') else 'Z';
MD_PAD_IO <= md_pad_o when (md_padoe_o = '1') else 'Z';
BLA1: FOR i in 31 downto 0 generate
wbs_cyc_i => m_wb_cyc_o,
wbs_stb_i => m_wb_stb_o,
wbs_we_i => m_wb_we_o,
- wbs_cti_i => (others => '0'),
- wbs_bte_i => (others => '0'),
+ wbs_cti_i => m_wb_cti_o,
+ wbs_bte_i => m_wb_bte_o,
wbs_ack_o => m_wb_ack_i,
-- wbs_rty_o => ,
wbs_err_o => m_wb_err_i,
wbm_rty_i => '0',
wbm_err_i => wb_err_o,
pci_clk_i => PCI_CLOCK,
- pci_rst_i => not PCI_RSTn,
+ pci_rst_i => PCI_RSTn,
pci_rst_o => pci_rst_o ,
pci_rst_oe_o => pci_rst_oe_o,
- pci_inta_i => not PCI_INTAn,
+ pci_inta_i => PCI_INTAn,
pci_inta_o => pci_inta_o,
pci_inta_oe_o => pci_inta_oe_o,
pci_req_o => pci_req_o,
pci_req_oe_o => pci_req_oe_o,
- pci_gnt_i => not PCI_GNTn,
- pci_frame_i => not PCI_FRAMEn,
+ pci_gnt_i => PCI_GNTn,
+ pci_frame_i => PCI_FRAMEn,
pci_frame_o => pci_frame_o,
pci_frame_oe_o => pci_frame_oe_o,
pci_irdy_oe_o => pci_irdy_oe_o,
pci_stop_oe_o => pci_stop_oe_o,
pci_ad_oe_o => pci_ad_oe_o,
pci_cbe_oe_o => pci_cbe_oe_o,
- pci_irdy_i => not PCI_IRDYn,
+ pci_irdy_i => PCI_IRDYn,
pci_irdy_o => pci_irdy_o,
pci_idsel_i => PCI_IDSEL,
- pci_devsel_i => not PCI_DEVSELn,
+ pci_devsel_i => PCI_DEVSELn,
pci_devsel_o => pci_devsel_o,
- pci_trdy_i => not PCI_TRDYn,
+ pci_trdy_i => PCI_TRDYn,
pci_trdy_o => pci_trdy_o,
- pci_stop_i => not PCI_STOPn,
+ pci_stop_i => PCI_STOPn,
pci_stop_o => pci_stop_o,
pci_ad_i => PCI_AD,
pci_ad_o => pci_ad_o,
- pci_cbe_i => not PCI_CBEn,
+ pci_cbe_i => PCI_CBEn,
pci_cbe_o => pci_cbe_o,
pci_par_i => PCI_PAR,
pci_par_o => pci_par_o,
pci_par_oe_o => pci_par_oe_o,
- pci_perr_i => not PCI_PERRn,
+ pci_perr_i => PCI_PERRn,
pci_perr_o => pci_perr_o,
pci_perr_oe_o => pci_perr_oe_o,
pci_serr_o => pci_serr_o,
mtx_clk_pad_i => MTX_CLK_PAD_I,
mtxd_pad_o => MTXD_PAD_O,
mtxen_pad_o => MTXEN_PAD_O,
- -- mtxerr_pad_o => ,
+ mtxerr_pad_o => LED_2,
mrx_clk_pad_i => MRX_CLK_PAD_I,
mrxd_pad_i => MRXD_PAD_I,
mrxdv_pad_i => MRXDV_PAD_I,
md_pad_i => MD_PAD_IO,
md_pad_o => md_pad_o,
md_padoe_o => md_padoe_o,
+ m_wb_cti_o => m_wb_cti_o,
+ m_wb_bte_o => m_wb_bte_o,
int_o => int_o
);
+--Inst_eth_cop: eth_cop PORT MAP(
+-- wb_clk_i => ,
+-- wb_rst_i => ,
+-- m1_wb_adr_i => ,
+-- m1_wb_sel_i => ,
+-- m1_wb_we_i => ,
+-- m1_wb_dat_o => ,
+-- m1_wb_dat_i => ,
+-- m1_wb_cyc_i => ,
+-- m1_wb_stb_i => ,
+-- m1_wb_ack_o => ,
+-- m1_wb_err_o => ,
+-- m2_wb_adr_i => ,
+-- m2_wb_sel_i => ,
+-- m2_wb_we_i => ,
+-- m2_wb_dat_o => ,
+-- m2_wb_dat_i => ,
+-- m2_wb_cyc_i => ,
+-- m2_wb_stb_i => ,
+-- m2_wb_ack_o => ,
+-- m2_wb_err_o => ,
+-- s1_wb_adr_o => ,
+-- s1_wb_sel_o => ,
+-- s1_wb_we_o => ,
+-- s1_wb_cyc_o => ,
+-- s1_wb_stb_o => ,
+-- s1_wb_ack_i => ,
+-- s1_wb_err_i => ,
+-- s1_wb_dat_i => ,
+-- s1_wb_dat_o => ,
+-- s2_wb_adr_o => ,
+-- s2_wb_sel_o => ,
+-- s2_wb_we_o => ,
+-- s2_wb_cyc_o => ,
+-- s2_wb_stb_o => ,
+-- s2_wb_ack_i => ,
+-- s2_wb_err_i => ,
+-- s2_wb_dat_i => ,
+-- s2_wb_dat_o =>
+--);
+
end architecture ethernet_arch;
projects / raggedstone / blobdiff