more LA signals

[raggedstone] / dhwk / source / top.vhd

diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
index 215b980cd582662ee273aaa65849ed0fbeb3b1f4..a148b3884ed09abd9c7dc5d29115a38fa0bd7813 100644 (file)
--- a/dhwk/source/top.vhd
+++ b/dhwk/source/top.vhd
@@ -20,6 +20,10 @@ entity dhwk is
 --             SPC_RDY_IN : In    std_logic;\r
              TAST_RESn : In    std_logic;\r
              TAST_SETn : In    std_logic;\r
 --             SPC_RDY_IN : In    std_logic;\r
              TAST_RESn : In    std_logic;\r
              TAST_SETn : In    std_logic;\r

+             LED_2 : out    std_logic;\r
+             LED_3 : out    std_logic;\r
+             LED_4 : out    std_logic;\r
+             LED_5 : out    std_logic;\r

               PCI_AD : InOut std_logic_vector (31 downto 0);\r
              PCI_PAR : InOut std_logic;\r
              PCI_DEVSELn : Out   std_logic;\r
               PCI_AD : InOut std_logic_vector (31 downto 0);\r
              PCI_PAR : InOut std_logic;\r
              PCI_DEVSELn : Out   std_logic;\r


@@ -28,6 +32,8 @@ entity dhwk is
              PCI_SERRn : Out   std_logic;\r
              PCI_STOPn : Out   std_logic;\r
              PCI_TRDYn : Out   std_logic;\r
              PCI_SERRn : Out   std_logic;\r
              PCI_STOPn : Out   std_logic;\r
              PCI_TRDYn : Out   std_logic;\r

+            PCI_REQn : Out std_logic;\r
+            PCI_GNTn : In std_logic;\r

 --             SERIAL_OUT : Out   std_logic;\r
 --             SPC_RDY_OUT : Out   std_logic;\r
              TB_IDSEL : Out   std_logic;\r
 --             SERIAL_OUT : Out   std_logic;\r
 --             SPC_RDY_OUT : Out   std_logic;\r
              TB_IDSEL : Out   std_logic;\r


@@ -86,6 +92,15 @@ architecture SCHEMATIC of dhwk is
    signal SPC_RDY_IN : std_logic;\r
    signal SERIAL_OUT : std_logic;\r
    signal SPC_RDY_OUT : std_logic;\r
    signal SPC_RDY_IN : std_logic;\r
    signal SERIAL_OUT : std_logic;\r
    signal SPC_RDY_OUT : std_logic;\r

+   signal watch_PCI_INTAn : std_logic;\r
+   signal watch_PCI_TRDYn : std_logic;\r
+   signal watch_PCI_STOPn : std_logic;\r
+   signal watch_PCI_SERRn : std_logic;\r
+   signal watch_PCI_PERRn : std_logic;\r
+   signal watch_PCI_REQn : std_logic;\r
+   signal control0       : std_logic_vector(35 downto 0);\r
+   signal data       : std_logic_vector(95 downto 0);\r
+   signal trig0      : std_logic_vector(31 downto 0);\r

 \r
    component MESS_1_TB\r
       Port ( DEVSELn : In    std_logic;\r
 \r
    component MESS_1_TB\r
       Port ( DEVSELn : In    std_logic;\r


@@ -201,7 +216,7 @@ architecture SCHEMATIC of dhwk is
              WRITE_XX7_6 : Out   std_logic );\r
    end component;\r
 \r
              WRITE_XX7_6 : Out   std_logic );\r
    end component;\r
 \r

-component fifo_generator_v3_2\r
+component dhwk_fifo\r

         port (\r
         clk: IN std_logic;\r
         din: IN std_logic_VECTOR(7 downto 0);\r
         port (\r
         clk: IN std_logic;\r
         din: IN std_logic_VECTOR(7 downto 0);\r


@@ -216,9 +231,92 @@ component fifo_generator_v3_2
         prog_full: OUT std_logic);\r
 end component;\r
 \r
         prog_full: OUT std_logic);\r
 end component;\r
 \r

+component icon\r
+port\r
+       (\r
+        control0    :   out std_logic_vector(35 downto 0)\r
+       );\r
+end component;\r
+\r
+  component ila\r
+    port\r
+    (\r
+      control     : in    std_logic_vector(35 downto 0);\r
+      clk         : in    std_logic;\r
+      data        : in    std_logic_vector(95 downto 0);\r
+      trig0       : in    std_logic_vector(31 downto 0)\r
+    );\r
+  end component;\r
+\r
+\r

 begin\r
 begin\r

+       watch_PCI_REQn <= '1';\r

        SERIAL_IN <= SERIAL_OUT;\r
        SPC_RDY_IN <= SPC_RDY_OUT;\r
        SERIAL_IN <= SERIAL_OUT;\r
        SPC_RDY_IN <= SPC_RDY_OUT;\r

+       LED_2 <= not PCI_RSTn;\r
+       LED_3 <= PCI_IDSEL;\r
+       LED_4 <= not PCI_FRAMEn;\r
+       LED_5 <= not watch_PCI_INTAn;\r
+       PCI_INTAn <= watch_PCI_INTAn;\r
+       trig0(31 downto 0) <= (\r
+               0 => watch_PCI_INTAn,\r
+               1 => R_FIFO_READn,\r
+               2 => R_FIFO_WRITEn,\r
+               3 => S_FIFO_READn,\r
+               4 => S_FIFO_WRITEn, \r
+               5 => PCI_RSTn,\r
+               16 => PCI_AD(0),\r
+               17 => PCI_AD(1),\r
+               18 => PCI_AD(2),\r
+               19 => PCI_AD(3),\r
+               20 => PCI_AD(4),\r
+               21 => PCI_AD(5),\r
+               22 => PCI_AD(6),\r
+               23 => PCI_AD(7),\r
+               27 => PCI_FRAMEn,\r
+               28 => PCI_CBEn(0),\r
+               29 => PCI_CBEn(1),\r
+               30 => PCI_CBEn(2),\r
+               31 => PCI_CBEn(3),\r
+               others => '0');\r
+\r
+       data(0) <= watch_PCI_INTAn;\r
+       data(1) <= R_EFn;\r
+       data(2) <= R_HFn;\r
+       data(3) <= R_FFn;\r
+       data(4) <= R_FIFO_READn;\r
+       data(5) <= R_FIFO_RESETn;\r
+       data(6) <= R_FIFO_RTn;\r
+       data(7) <= R_FIFO_WRITEn;\r
+       data(8) <= S_EFn;\r
+       data(9) <= S_HFn;\r
+       data(10) <= S_FFn;\r
+       data(11) <= S_FIFO_READn;\r
+       data(12) <= S_FIFO_RESETn;\r
+       data(13) <= S_FIFO_RTn;\r
+       data(14) <= S_FIFO_WRITEn;\r
+       data(15) <= SERIAL_IN;\r
+       data(16) <= SPC_RDY_IN;\r
+       data(17) <= SERIAL_OUT;\r
+       data(18) <= SPC_RDY_OUT;\r
+       data(26 downto 19) <= S_FIFO_Q_OUT;\r
+       data(34 downto 27) <= R_FIFO_Q_OUT;\r
+       data(66 downto 35) <= PCI_AD(31 downto 0);\r
+       data(70 downto 67) <= PCI_CBEn(3 downto 0);\r
+       data(71) <= PCI_FRAMEn;\r
+       data(72) <= PCI_IDSEL;\r
+       PCI_TRDYn <= watch_PCI_TRDYn;\r
+       data(73) <= watch_PCI_TRDYn;\r
+       data(74) <= PCI_IRDYn;\r
+       PCI_STOPn <= watch_PCI_STOPn;\r
+       data(75) <= watch_PCI_STOPn;\r
+       PCI_SERRn <= watch_PCI_SERRn;\r
+       data(76) <= watch_PCI_SERRn;\r
+       PCI_PERRn <= watch_PCI_PERRn;\r
+       data(77) <= watch_PCI_PERRn;\r
+       PCI_REQn <= watch_PCI_REQn;\r
+       data(78) <= watch_PCI_REQn;\r
+       data(79) <= PCI_GNTn;\r

 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
 \r
    I19 : MESS_1_TB\r
       Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r


@@ -239,7 +337,7 @@ begin
                  READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
                  TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
                  TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
                  READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
                  TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
                  TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r

-                 INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );\r
+                 INTAn=>INTAn, PCI_INTAn=>watch_PCI_INTAn);\r

    I14 : FIFO_CONTROL\r
       Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
                  FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
    I14 : FIFO_CONTROL\r
       Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
                  FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r


@@ -275,9 +373,9 @@ begin
                  PCI_PAR=>PCI_PAR,\r
                  AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
                  DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
                  PCI_PAR=>PCI_PAR,\r
                  AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
                  DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r

-                 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
-                 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
-                 PCI_TRDYn=>PCI_TRDYn,\r
+                 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>watch_PCI_PERRn,\r
+                 PCI_SERRn=>watch_PCI_SERRn, PCI_STOPn=>watch_PCI_STOPn,\r
+                 PCI_TRDYn=>watch_PCI_TRDYn,\r

                  READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
                  READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
                  READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r
                  READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
                  READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
                  READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r


@@ -288,7 +386,7 @@ begin
                  WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
                  WRITE_XX7_6=>WRITE_XX7_6 );\r
 \r
                  WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
                  WRITE_XX7_6=>WRITE_XX7_6 );\r
 \r

-receive_fifo : fifo_generator_v3_2\r
+receive_fifo : dhwk_fifo\r

                 port map (\r
                         clk => PCI_CLOCK,\r
                         din => R_FIFO_D_IN,\r
                 port map (\r
                         clk => PCI_CLOCK,\r
                         din => R_FIFO_D_IN,\r


@@ -300,7 +398,7 @@ receive_fifo : fifo_generator_v3_2
                         full => R_FFn,\r
                         prog_full => R_HFn);\r
 \r
                         full => R_FFn,\r
                         prog_full => R_HFn);\r
 \r

-send_fifo : fifo_generator_v3_2\r
+send_fifo : dhwk_fifo\r

                 port map (\r
                         clk => PCI_CLOCK,\r
                         din => S_FIFO_D_IN,\r
                 port map (\r
                         clk => PCI_CLOCK,\r
                         din => S_FIFO_D_IN,\r


@@ -311,4 +409,19 @@ send_fifo : fifo_generator_v3_2
                         empty => S_EFn,\r
                         full => S_FFn,\r
                         prog_full => S_HFn);\r
                         empty => S_EFn,\r
                         full => S_FFn,\r
                         prog_full => S_HFn);\r

+\r
+  i_icon : icon\r
+      port map\r
+          (\r
+               control0    => control0\r
+         );\r
+\r
+  i_ila : ila\r
+    port map\r
+    (\r
+      control   => control0,\r
+      clk       => PCI_CLOCK,\r
+      data      => data,\r
+      trig0     => trig0\r
+    );\r

 end SCHEMATIC;\r
 end SCHEMATIC;\r