+ SERIAL_IN <= SERIAL_OUT;\r
+ SPC_RDY_IN <= SPC_RDY_OUT;\r
+ LED_2 <= TAST_RESn;\r
+ LED_3 <= TAST_SETn;\r
+ LED_4 <= '0';\r
+ LED_5 <= not watch;\r
+ PCI_INTAn <= watch;\r
+ trig0(7 downto 0) <= (others => '0');\r
+ data(31 downto 0) <= PCI_AD(31 downto 0);\r
+ data(32) <= watch;\r
+ \r
+ data(33) <= R_EFn;\r
+ data(34) <= R_HFn;\r
+ data(35) <= R_FFn;\r
+ data(36) <= R_FIFO_READn;\r
+ data(37) <= R_FIFO_RESETn;\r
+ data(38) <= R_FIFO_RTn;\r
+ data(39) <= R_FIFO_WRITEn;\r
+ data(40) <= S_EFn;\r
+ data(41) <= S_HFn;\r
+ data(42) <= S_FFn;\r
+ data(43) <= S_FIFO_READn;\r
+ data(44) <= S_FIFO_RESETn;\r
+ data(45) <= S_FIFO_RTn;\r
+ data(46) <= S_FIFO_WRITEn;\r
+ data(47) <= SERIAL_IN;\r
+ data(48) <= SPC_RDY_IN;\r
+ data(49) <= SERIAL_OUT;\r
+ data(50) <= SPC_RDY_OUT;\r