this file is no longer autogenerated
[raggedstone] / dhwk / source / pci / config_space_header.vhd
index 722b931cac03ea21acff8726c08c235b105b4267..1adc96a2ba391ec57cffa0c9b7cd510bb887189b 100644 (file)
@@ -1,5 +1,3 @@
--- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007
-
 LIBRARY ieee;
 
 USE ieee.std_logic_1164.ALL;
@@ -38,6 +36,80 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
 
         signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0);
 
+        signal CONF_STATUS :std_logic_vector(31 downto 16);
+        signal CONF_COMMAND :std_logic_vector(15 downto 0);
+
+        -- PCI Configuration Space Header
+        --
+        -- \ Bit
+        -- \
+        --Address |31 24|23 16|15 8|7 0|
+        -----------------------------------------------------------------
+        --00 |Device ID |Vendor ID |
+        --04 |Status |Command |
+        --08 |Class Code |Revision ID |
+        --0C |BIST |Header Type |Latency T. |Cache L.S. |
+        --10-24 |Base Address Register |
+        --28 |Cardbus CIS Pointer |
+        --2C |Subsystem ID |Subsystem Vendor ID |
+        --30 |Expansion ROM Base Address |
+        --34 |Reserved |
+        --38 |Reserved |
+        --3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line |
+        --40-FF | |
+        -----------------------------------------------------------------
+
+
+        --PCI Bus Commands
+        --C/BE[3..0] Command Type
+        --------------------------------------
+        -- 0000 Interrupt Acknowledge
+        -- 0001 Special Cycle
+        -- 0010 I/O Read
+        -- 0011 I/O Write
+        -- 0100 Reserved
+        -- 0101 Reserved
+        -- 0110 Memory Read
+        -- 0111 Memory Write
+        --
+        -- 1000 Reserved
+        -- 1001 Reserved
+        -- 1010 Configuration Read
+        -- 1011 Configuration Write
+        -- 1100 Memory Read Multiple
+        -- 1101 Dual Address Cycle
+        -- 1110 Memory Read Line
+        -- 1111 Memory Write and Invalidate
+
+
+        --PCI Byte Enable
+        --C/BE[3..0] gueltige Datenbits
+        -------------------------------
+        -- 0000 AD 31..0
+        -- 1000 AD 23..0
+        -- 1100 AD 15..0
+        -- 1110 AD 7..0
+
+        constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";
+        constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";
+        constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";
+        constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";
+        constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";
+        constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";
+        constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";
+        constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";
+        constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";
+        constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";
+        constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";
+        constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";
+        constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";
+        constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";
+        constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";
+        constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
+
+        signal CONFIG_ADDR :std_logic_vector(7 downto 0);
+        signal CONFIG_WRITE :std_logic_vector(3 downto 0);
+
         SIGNAL gnd : std_logic := '0';
         SIGNAL vcc : std_logic := '1';
 
@@ -45,43 +117,14 @@ architecture SCHEMATIC of CONFIG_SPACE_HEADER is
         signal CONF_WR_10H : std_logic;
         signal CONF_WR_3CH : std_logic;
         signal CONF_READ_SEL : std_logic_vector (2 downto 0);
-        signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
         signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
         signal CONF_DATA_08H : std_logic_vector (31 downto 0);
         signal CONF_DATA_00H : std_logic_vector (31 downto 0);
 
-        component CONFIG_RD_0
-                Port ( ADDR_REG : In std_logic_vector (31 downto 0);
-                       CF_RD_COM : In std_logic;
-                       READ_SEL : Out std_logic_vector (2 downto 0) );
-        end component;
-
-        component CONFIG_WR_0
-                Port ( ADDR_REG : In std_logic_vector (31 downto 0);
-                       CF_WR_COM : In std_logic;
-                       IRDY_REGn : In std_logic;
-                       TRDYn : In std_logic;
-                       CONF_WR_04H : Out std_logic;
-                       CONF_WR_10H : Out std_logic;
-                       CONF_WR_3CH : Out std_logic );
-        end component;
-
-        component CONFIG_04H
-                Port ( AD_REG : In std_logic_vector (31 downto 0);
-                       CBE_REGn : In std_logic_vector (3 downto 0);
-                       CONF_WR_04H : In std_logic;
-                       PCI_CLOCK : In std_logic;
-                       PCI_RSTn : In std_logic;
-                       PERR : In std_logic;
-                       SERR : In std_logic;
-                       CONF_DATA_04H : Out std_logic_vector (31 downto 0) );
-        end component;
-
 begin
         CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
         CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
-
-        CONF_DATA_04H <= CONF_DATA_04H_DUMMY;
+        CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND;
 
         CONF_MAX_LAT <= X"00";
         CONF_MIN_GNT <= X"00";
@@ -97,22 +140,6 @@ begin
         CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE
         CONF_DATA_10H <= CONF_BAS_ADDR_REG;
 
-        I9 : CONFIG_RD_0
-        Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
-                   CF_RD_COM=>CF_RD_COM,
-                   READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
-        I8 : CONFIG_WR_0
-        Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
-                   CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,
-                   TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,
-                   CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );
-        I2 : CONFIG_04H
-        Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
-        CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
-        CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,
-        PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,
-        CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );
-
         process (PCI_CLOCK,PCI_RSTn)
         begin
         if PCI_RSTn = '0' then
@@ -165,4 +192,153 @@ begin
                 end if;
         end if;
         end process;
+
+        --*******************************************************************
+        --************* PCI Configuration Space Header "STATUS" *************
+        --*******************************************************************
+
+        CONF_STATUS(20 downto 16) <= "00000";-- Reserved
+        CONF_STATUS(21 ) <= '0';-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz
+        CONF_STATUS(22 ) <= '0';-- MAS/TAR: "R_O"
+        CONF_STATUS(23 ) <= '0';-- ???/???: "R_O" : fast back-to-back
+        CONF_STATUS(24 ) <= '0';-- Master :
+        --CONF_STATUS(26 downto 25) <= "00";-- Mas/Tar: "R_O" : timing fast for "DEVSEL"
+        CONF_STATUS(26 downto 25) <= "01";-- Mas/Tar: "R_O" : timing medium for "DEVSEL"
+        --CONF_STATUS(26 downto 25) <= "10";-- Mas/Tar: "R_O" : timing slow for "DEVSEL"
+        --CONF_STATUS(26 downto 25) <= "11";-- Mas/Tar: "R_O" : reserved
+        CONF_STATUS(27 ) <= '0';-- Target : "R_W" : Taget-Abort
+        CONF_STATUS(28 ) <= '0';-- Master : "R_W" : Taget-Abort
+        CONF_STATUS(29 ) <= '0';-- Master : "R_W" : Master-Abort
+        --CONF_STATUS(30 ) <= SERR;-- Mas/Tar: "R_W" : SERR
+        --CONF_STATUS(31 ) <= PERR;-- Mas/Tar: "R_W" : PERR
+
+        process (PCI_CLOCK,PCI_RSTn)
+        begin
+        if PCI_RSTn = '0' then
+                CONF_STATUS(30) <= '0';
+                CONF_STATUS(31) <= '0';
+
+        elsif (rising_edge(PCI_CLOCK)) then
+                if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then
+                        CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30));
+                        CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));
+
+                else
+                        CONF_STATUS(30) <= SERR or CONF_STATUS(30);
+                        CONF_STATUS(31) <= PERR or CONF_STATUS(31);
+
+                end if;
+        end if;
+        end process;
+
+        --*******************************************************************
+        --*********** PCI Configuration Space Header "COMMAND" **************
+        --*******************************************************************
+
+        -- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???
+        -- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???
+        -- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus
+        -- CONF_COMMAND( 3) <= '0';-- Special Cycle ???
+        -- CONF_COMMAND( 4) <= '0';-- Master ???
+        -- CONF_COMMAND( 5) <= '0';-- VGA ???
+        -- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable
+        CONF_COMMAND( 7) <= '0';-- address/data stepping ???
+        -- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"
+        -- CONF_COMMAND( 9) <= '0';-- fast back-to-back
+        -- CONF_COMMAND(10) <= '0';-- Reserved
+        -- CONF_COMMAND(11) <= '0';-- Reserved
+        -- CONF_COMMAND(12) <= '0';-- Reserved
+        -- CONF_COMMAND(13) <= '0';-- Reserved
+        -- CONF_COMMAND(14) <= '0';-- Reserved
+        -- CONF_COMMAND(15) <= '0';-- Reserved
+
+        process (PCI_CLOCK,PCI_RSTn)
+        begin
+                if PCI_RSTn = '0' then
+                        CONF_COMMAND(15 downto 8) <= (others =>'0');
+                        CONF_COMMAND( 6 downto 0) <= (others =>'0');
+
+                elsif (rising_edge(PCI_CLOCK)) then
+
+                        if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then
+                                CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8);
+                        else
+                                CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8);
+                        end if;
+
+                        if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then
+                                CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0);
+                        else
+                                CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0);
+                        end if;
+                end if;
+        end process;
+
+
+        --*******************************************************************
+        --******************* PCI Write Configuration Address ***************
+        --*******************************************************************
+
+        CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
+
+
+        process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR)
+        begin
+
+                if CF_WR_COM = '1' and IRDY_REGn = '0' and TRDYn = '0' then
+
+                        if CONFIG_ADDR = X"04" then
+                                CONFIG_WRITE <= "0001";
+
+                        elsif CONFIG_ADDR = X"10" then
+                                CONFIG_WRITE <= "0010";
+
+                        elsif CONFIG_ADDR = X"3C" then
+                                CONFIG_WRITE <= "0100";
+
+                        -- elsif CONFIG_ADDR = X"40" then
+                        --         CONFIG_WRITE <= "1000";
+                        else
+                                CONFIG_WRITE <= "0000";
+                        end if;
+                else
+                        CONFIG_WRITE <= "0000";
+                end if;
+        end process;
+
+        CONF_WR_04H <= CONFIG_WRITE(0);
+        CONF_WR_10H <= CONFIG_WRITE(1);
+        CONF_WR_3CH <= CONFIG_WRITE(2);
+        --CONF_WR_40H <= CONFIG_WRITE(3);
+
+        process (CF_RD_COM, CONFIG_ADDR)
+        begin
+
+                if CF_RD_COM = '1' then
+                        if CONFIG_ADDR = X"00" then
+                                CONF_READ_SEL <= "000";
+
+                        elsif CONFIG_ADDR = X"04" then
+                                CONF_READ_SEL <= "001";
+
+                        elsif CONFIG_ADDR = X"08" then
+                                CONF_READ_SEL <= "010";
+
+                        elsif CONFIG_ADDR = X"10" then
+                                CONF_READ_SEL <= "011";
+
+                        elsif CONFIG_ADDR = X"3C" then
+                                CONF_READ_SEL <= "100";
+
+                        elsif CONFIG_ADDR = X"40" then
+                                CONF_READ_SEL <= "101";
+
+                        else
+                                CONF_READ_SEL <= "111";
+                        end if;
+                else
+                        CONF_READ_SEL <= "111";
+                end if;
+        end process;
+
 end SCHEMATIC;
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