]cvsignore and chipscope file for EDK project

[raggedstone] / dhwk / source / ser_par_con.vhd

diff --git a/dhwk/source/ser_par_con.vhd b/dhwk/source/ser_par_con.vhd
index 7c6978de192f1958b1e7d9a7ae28e0370fb792f8..6c45577a523436f3c3dbef4e37d4a19a1b83786a 100644 (file)
--- a/dhwk/source/ser_par_con.vhd
+++ b/dhwk/source/ser_par_con.vhd
@@ -1,4 +1,4 @@
--- $Id: ser_par_con.vhd,v 1.1 2007-03-11 08:55:29 sithglan Exp $
+-- $Id: ser_par_con.vhd,v 1.4 2007-03-11 13:23:11 sithglan Exp $
 
 library ieee;
 use ieee.std_logic_1164.all;
@@ -46,7 +46,7 @@ begin
 
         process(PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         if ("0000" < COUNT) then
                                 COUNT <= COUNT - 1;
                         end if;
@@ -129,7 +129,7 @@ begin
 
         process(PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;
                 end if;
         end process;
@@ -137,7 +137,7 @@ begin
 
         process(PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         if (RESET = '1') then
                                 STARTBIT <= "0000";
                         else