perl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1'/rising_edge(PCI_CLOCK)/" *.vhd

[raggedstone] / dhwk / source / pci / fifo_io_control.vhd

diff --git a/dhwk/source/pci/fifo_io_control.vhd b/dhwk/source/pci/fifo_io_control.vhd
index f9faba372b5e79d7a70ea45aa347987cd7e16cde..43f3a43bc7e5f7e12da7010add5ce226a516c2ba 100644 (file)
--- a/dhwk/source/pci/fifo_io_control.vhd
+++ b/dhwk/source/pci/fifo_io_control.vhd
@@ -1,4 +1,4 @@
--- $Id: fifo_io_control.vhd,v 1.1 2007-03-11 08:55:29 sithglan Exp $
+-- $Id: fifo_io_control.vhd,v 1.2 2007-03-11 09:14:58 sithglan Exp $
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -35,7 +35,7 @@ begin
 
         process (PCI_CLOCK)
         begin
-                if (PCI_CLOCK'event and PCI_CLOCK = '1') then
+                if (rising_edge(PCI_CLOCK)) then
                         if (RESET = '1') then
                                 S_FIFO_WRITEn <= '1';
                                 SIG_S_ERROR <= '0';